Searched refs:CPG_PLLECR (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/renesas/
A D	clk-sh73a0.c	29 #define CPG_PLLECR 0xd0 macro 111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
A D	rcar-gen3-cpg.c	29 #define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */ macro 139 pll_clk->pllecr_reg = base + CPG_PLLECR; in cpg_pll_clk_register()

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