1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_CPU_CA53_CFG_MASKS_H_ 14 #define ASIC_REG_CPU_CA53_CFG_MASKS_H_ 15 16 /* 17 ***************************************** 18 * CPU_CA53_CFG (Prototype: CA53_CFG) 19 ***************************************** 20 */ 21 22 /* CPU_CA53_CFG_ARM_CFG */ 23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0 24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3 25 #define CPU_CA53_CFG_ARM_CFG_END_SHIFT 4 26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30 27 #define CPU_CA53_CFG_ARM_CFG_TE_SHIFT 8 28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300 29 #define CPU_CA53_CFG_ARM_CFG_VINITHI_SHIFT 12 30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000 31 32 /* CPU_CA53_CFG_RST_ADDR_LSB */ 33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0 34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF 35 36 /* CPU_CA53_CFG_RST_ADDR_MSB */ 37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0 38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF 39 40 /* CPU_CA53_CFG_ARM_RST_CONTROL */ 41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 42 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 43 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 44 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 45 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 46 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 47 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 48 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 49 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 50 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 51 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 52 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 53 54 /* CPU_CA53_CFG_ARM_AFFINITY */ 55 #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_SHIFT 0 56 #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_MASK 0xFF 57 #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_SHIFT 8 58 #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_MASK 0xFF00 59 60 /* CPU_CA53_CFG_ARM_DISABLE */ 61 #define CPU_CA53_CFG_ARM_DISABLE_CP15S_SHIFT 0 62 #define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK 0x3 63 #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_SHIFT 4 64 #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_MASK 0x30 65 #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_SHIFT 8 66 #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_MASK 0x100 67 #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_SHIFT 9 68 #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_MASK 0x200 69 70 /* CPU_CA53_CFG_ARM_GIC_PERIPHBASE */ 71 #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_SHIFT 0 72 #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_MASK 0x3FFFFF 73 74 /* CPU_CA53_CFG_ARM_GIC_IRQ_CFG */ 75 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_SHIFT 0 76 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK 0x3 77 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_SHIFT 4 78 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_MASK 0x30 79 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_SHIFT 8 80 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_MASK 0x300 81 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_SHIFT 12 82 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_MASK 0x3000 83 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_SHIFT 16 84 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_MASK 0x30000 85 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_SHIFT 20 86 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_MASK 0x300000 87 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_SHIFT 24 88 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_MASK 0x3000000 89 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_SHIFT 31 90 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_MASK 0x80000000 91 92 /* CPU_CA53_CFG_ARM_PWR_MNG */ 93 #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_SHIFT 0 94 #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_MASK 0x1 95 #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_SHIFT 1 96 #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_MASK 0x2 97 #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_SHIFT 2 98 #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_MASK 0x4 99 #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_SHIFT 3 100 #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_MASK 0x8 101 #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_SHIFT 4 102 #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_MASK 0x30 103 #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_SHIFT 8 104 #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_MASK 0x300 105 #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_SHIFT 12 106 #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_MASK 0x3000 107 108 /* CPU_CA53_CFG_ARB_DBG_ROM_ADDR */ 109 #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_SHIFT 0 110 #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_MASK 0xFFFFFFF 111 #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_SHIFT 31 112 #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_MASK 0x80000000 113 114 /* CPU_CA53_CFG_ARM_DBG_MODES */ 115 #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_SHIFT 0 116 #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_MASK 0x3 117 #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_SHIFT 4 118 #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_MASK 0x30 119 #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_SHIFT 8 120 #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_MASK 0x300 121 #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_SHIFT 12 122 #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_MASK 0x3000 123 #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_SHIFT 16 124 #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_MASK 0x30000 125 126 /* CPU_CA53_CFG_ARM_PWR_STAT_0 */ 127 #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_SHIFT 0 128 #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_MASK 0x1 129 #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_SHIFT 1 130 #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_MASK 0x2 131 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_SHIFT 4 132 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_MASK 0x30 133 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_SHIFT 8 134 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_MASK 0x300 135 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_SHIFT 12 136 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_MASK 0x1000 137 #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_SHIFT 13 138 #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_MASK 0x2000 139 #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_SHIFT 16 140 #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_MASK 0x30000 141 142 /* CPU_CA53_CFG_ARM_PWR_STAT_1 */ 143 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_SHIFT 0 144 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_MASK 0x3 145 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_SHIFT 4 146 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_MASK 0x30 147 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_SHIFT 8 148 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_MASK 0x300 149 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_SHIFT 12 150 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_MASK 0x3000 151 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_SHIFT 16 152 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_MASK 0x30000 153 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_SHIFT 20 154 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_MASK 0x300000 155 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_SHIFT 24 156 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_MASK 0x1000000 157 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_SHIFT 25 158 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_MASK 0x2000000 159 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_SHIFT 26 160 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_MASK 0x4000000 161 162 /* CPU_CA53_CFG_ARM_DBG_STATUS */ 163 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_SHIFT 0 164 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_MASK 0x3 165 #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_SHIFT 4 166 #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_MASK 0x30 167 #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_SHIFT 8 168 #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_MASK 0x300 169 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_SHIFT 12 170 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_MASK 0x3000 171 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_SHIFT 16 172 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_MASK 0x30000 173 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_SHIFT 20 174 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_MASK 0x300000 175 176 /* CPU_CA53_CFG_ARM_MEM_ATTR */ 177 #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_SHIFT 0 178 #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_MASK 0xFF 179 #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_SHIFT 8 180 #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_MASK 0xFF00 181 #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_SHIFT 16 182 #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_MASK 0x10000 183 #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_SHIFT 20 184 #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_MASK 0x100000 185 186 /* CPU_CA53_CFG_ARM_PMU */ 187 #define CPU_CA53_CFG_ARM_PMU_EVENT_SHIFT 0 188 #define CPU_CA53_CFG_ARM_PMU_EVENT_MASK 0x3FFFFFFF 189 190 #endif /* ASIC_REG_CPU_CA53_CFG_MASKS_H_ */ 191