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Searched refs:CRTC (Results 1 – 25 of 41) sorted by relevance

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/linux/drivers/gpu/drm/nouveau/dispnv04/
A Dcrtc.c60 crtcstate->CRTC[index]); in crtc_wr_cio_state()
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
390 regp->CRTC[NV_CIO_CRE_42] = in nv_crtc_mode_set_vga()
494 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); in nv_crtc_mode_set_regs()
519 regp->CRTC[NV_CIO_CRE_53] = 0; in nv_crtc_mode_set_regs()
520 regp->CRTC[NV_CIO_CRE_54] = 0; in nv_crtc_mode_set_regs()
532 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; in nv_crtc_mode_set_regs()
542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; in nv_crtc_mode_set_regs()
575 regp->CRTC[NV_CIO_CRE_86] = 0x1; in nv_crtc_mode_set_regs()
681 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; in nv_crtc_save()
[all …]
A Dcursor.c34 crtcstate->CRTC[index]); in crtc_wr_cio_state()
45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = in nv04_cursor_set_offset()
48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = in nv04_cursor_set_offset()
51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= in nv04_cursor_set_offset()
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; in nv04_cursor_set_offset()
A Dtvnv04.c112 state->CRTC[NV_CIO_CRE_49] |= 0x10; in nv04_tv_bind()
114 state->CRTC[NV_CIO_CRE_49] &= ~0x10; in nv04_tv_bind()
117 state->CRTC[NV_CIO_CRE_LCD__INDEX]); in nv04_tv_bind()
119 state->CRTC[NV_CIO_CRE_49]); in nv04_tv_bind()
A Ddfp.c109 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &= in nv04_dfp_disable()
252 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
253 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
A Ddisp.h23 uint8_t CRTC[0xa0]; member
A Dtvnv17.c403 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ in nv17_tv_prepare()
469 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ in nv17_tv_mode_set()
470 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ in nv17_tv_mode_set()
/linux/drivers/video/fbdev/matrox/
A Dmatroxfb_misc.c304 hw->CRTC[0] = ht-4; in matroxfb_vgaHWinit()
305 hw->CRTC[1] = hd; in matroxfb_vgaHWinit()
306 hw->CRTC[2] = hd; in matroxfb_vgaHWinit()
308 hw->CRTC[4] = hs; in matroxfb_vgaHWinit()
310 hw->CRTC[6] = vt & 0xFF; in matroxfb_vgaHWinit()
319 hw->CRTC[8] = 0x00; in matroxfb_vgaHWinit()
323 hw->CRTC[9] |= 0x80; in matroxfb_vgaHWinit()
325 hw->CRTC[i] = 0x00; in matroxfb_vgaHWinit()
330 hw->CRTC[20] = 0x00; in matroxfb_vgaHWinit()
333 hw->CRTC[23] = 0xC3; in matroxfb_vgaHWinit()
[all …]
/linux/drivers/video/fbdev/
A Dneofb.c298 par->CRTC[8] = 0x00; in vgaHWInit()
302 par->CRTC[9] |= 0x80; in vgaHWInit()
304 par->CRTC[10] = 0x00; in vgaHWInit()
305 par->CRTC[11] = 0x00; in vgaHWInit()
306 par->CRTC[12] = 0x00; in vgaHWInit()
307 par->CRTC[13] = 0x00; in vgaHWInit()
308 par->CRTC[14] = 0x00; in vgaHWInit()
309 par->CRTC[15] = 0x00; in vgaHWInit()
314 par->CRTC[20] = 0x00; in vgaHWInit()
317 par->CRTC[23] = 0xC3; in vgaHWInit()
[all …]
/linux/drivers/video/fbdev/savage/
A Dsavagefb_driver.c184 reg->CRTC[0x08] = 0x00; in vgaHWInit()
188 reg->CRTC[0x09] |= 0x80; in vgaHWInit()
190 reg->CRTC[0x0a] = 0x00; in vgaHWInit()
191 reg->CRTC[0x0b] = 0x00; in vgaHWInit()
192 reg->CRTC[0x0c] = 0x00; in vgaHWInit()
193 reg->CRTC[0x0d] = 0x00; in vgaHWInit()
194 reg->CRTC[0x0e] = 0x00; in vgaHWInit()
195 reg->CRTC[0x0f] = 0x00; in vgaHWInit()
200 reg->CRTC[0x14] = 0x00; in vgaHWInit()
203 reg->CRTC[0x17] = 0xc3; in vgaHWInit()
[all …]
A Dsavagefb.h155 unsigned char CRTC[25]; /* Crtc Controller */ member
/linux/Documentation/gpu/
A Dkms-properties.csv61 armada,CRTC,"""CSC_YUV""",ENUM,"{ ""Auto"" , ""CCIR601"", ""CCIR709"" }",CRTC,TBD
62 ,,"""CSC_RGB""",ENUM,"{ ""Auto"", ""Computer system"", ""Studio"" }",CRTC,TBD
72 exynos,CRTC,“mode”,ENUM,"{ ""normal"", ""blank"" }",CRTC,TBD
90 omap,Generic,“zorder”,RANGE,"Min=0, Max=3","CRTC, Plane",TBD
A Ddrm-kms.rst61 details. One or more (or even no) planes feed their pixel data into a CRTC
62 (represented by :c:type:`struct drm_crtc <drm_crtc>`, see `CRTC Abstraction`_)
70 to figure out which connections between a CRTC and a connector are possible, and
75 A CRTC can be connected to multiple encoders, and for an active CRTC there must
140 the CRTC and any encoders. Often for drivers with bridges there's no code left
309 CRTC Abstraction
315 CRTC Functions Reference
521 Standard CRTC Properties
525 :doc: standard CRTC properties
A Dvc4.rst15 Pixel Valve (DRM CRTC)
19 :doc: VC4 CRTC module
A Ddrm-uapi.rst471 CRTC index
474 CRTC's have both an object ID and an index, and they are not the same thing.
475 The index is used in cases where a densely packed identifier for a CRTC is
476 needed, for instance a bitmask of CRTC's. The member possible_crtcs of struct
479 DRM_IOCTL_MODE_GETRESOURCES populates a structure with an array of CRTC ID's,
480 and the CRTC index is its position in this array.
A Ddrm-kms-helpers.rst20 helpers. Old drivers still often use the legacy CRTC helpers. They both share
430 Legacy CRTC/Modeset Helper Functions Reference
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_hwseq.h110 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
111 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
117 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
122 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
128 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
133 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
145 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
155 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
156 HWSEQ_PHYPLL_REG_LIST(CRTC), \
168 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
[all …]
A Ddce_transform.h99 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
103 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
104 SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
164 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
170 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
A Ddce_ipp.h58 SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c147 IRQ_REG_ENTRY(CRTC, reg_num,\
155 IRQ_REG_ENTRY(CRTC, reg_num,\
/linux/drivers/usb/misc/sisusbvga/
A Dsisusb_struct.h74 unsigned char CRTC[0x19]; member
/linux/Documentation/devicetree/bindings/display/armada/
A Dmarvell,dove-lcd.txt1 Device Tree bindings for Armada DRM CRTC driver
/linux/include/video/
A Dneomagic.h129 unsigned char CRTC[25]; /* Crtc Controller */ member
/linux/drivers/gpu/drm/sti/
A DNOTES47 FB & planes Cursor CRTC Encoders Bridges/Connectors
/linux/Documentation/devicetree/bindings/display/rockchip/
A Drockchip-vop.yaml43 the CRTC gamma LUT address.
/linux/drivers/video/fbdev/sis/
A Dvstruct.h136 unsigned char CRTC[0x19]; member

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