| /linux/drivers/scsi/aacraid/ |
| A D | aacraid.h | 1082 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1083 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1084 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
1085 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
1144 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
1145 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
1146 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
1162 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
1163 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
1210 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) argument
[all …]
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| /linux/drivers/dma/ |
| A D | txx9dmac.c | 296 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
308 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
519 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
545 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
546 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
549 csr = channel32_readl(dc, CSR); in txx9dmac_scan_descriptors()
550 channel32_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
611 csr = channel_readl(dc, CSR); in txx9dmac_chan_tasklet()
629 channel_readl(dc, CSR)); in txx9dmac_chan_interrupt()
[all …]
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| A D | txx9dmac.h | 78 TXX9_DMA_REG32(CSR); /* Channel Status Register */
88 u32 CSR; member
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | xgene.txt | 36 - reg : shall be a list of address and length pairs describing the CSR
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
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| /linux/drivers/staging/qlge/ |
| A D | qlge_mpi.c | 9 tmp = qlge_read32(qdev, CSR); in qlge_unpause_mpi_risc()
13 qlge_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in qlge_unpause_mpi_risc()
23 qlge_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in qlge_pause_mpi_risc()
25 tmp = qlge_read32(qdev, CSR); in qlge_pause_mpi_risc()
39 qlge_write32(qdev, CSR, CSR_CMD_SET_RST); in qlge_hard_reset_mpi_risc()
41 tmp = qlge_read32(qdev, CSR); in qlge_hard_reset_mpi_risc()
43 qlge_write32(qdev, CSR, CSR_CMD_CLR_RST); in qlge_hard_reset_mpi_risc()
170 if (qlge_read32(qdev, CSR) & CSR_HRI) in qlge_exec_mb_cmd()
189 qlge_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in qlge_exec_mb_cmd()
513 qlge_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in qlge_mpi_handler()
[all …]
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| /linux/arch/arm/plat-omap/ |
| A D | dma.c | 411 p->dma_read(CSR, lch); in omap_enable_channel_irq()
413 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_enable_channel_irq()
425 p->dma_read(CSR, lch); in omap_disable_channel_irq()
427 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_disable_channel_irq()
821 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
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| /linux/drivers/soc/litex/ |
| A D | Kconfig | 15 LiteX CSR access and provides common litex_[read|write]*
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| /linux/Documentation/devicetree/bindings/pci/ |
| A D | altera-pcie-msi.txt | 8 "csr": CSR registers
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| A D | mediatek-pcie.txt | 23 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
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| /linux/arch/arm/mach-omap1/ |
| A D | dma.c | 59 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
219 l = dma_read(CSR, lch); in omap1_clear_dma()
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| /linux/Documentation/devicetree/bindings/soc/litex/ |
| A D | litex,soc-controller.yaml | 12 Its purpose is to verify LiteX CSR (Control&Status Register) access
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| /linux/arch/arm/mach-omap2/ |
| A D | dma.c | 56 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
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| /linux/Documentation/devicetree/bindings/misc/ |
| A D | idt_89hpesx.txt | 1 EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| A D | pinctrl-sirf.txt | 1 CSR SiRFprimaII pinmux controller
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| /linux/Documentation/arm/ |
| A D | ixp4xx.rst | 39 require the use of Intel's proprietary CSR software:
140 the CSR or a WiFi card and a ramdisk that BOOTPs and then does
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| A D | riscv,cpu-intc.txt | 14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
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| /linux/Documentation/admin-guide/perf/ |
| A D | xgene-pmu.rst | 9 interrupt and status CSR region.
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| /linux/Documentation/driver-api/rapidio/ |
| A D | rapidio.rst | 256 device by writing into the Host Device ID Lock CSR. It does this to ensure that
262 is written into the device's Base Device ID CSR.
279 into device's Component Tag CSR. That unique value is used by the error
291 in the system, it sets the Discovered bit in the Port General Control CSR
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| /linux/include/linux/ |
| A D | omap-dma.h | 153 CSDP, CCR, CICR, CSR, enumerator
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| /linux/drivers/dma/ti/ |
| A D | omap-dma.c | 386 omap_dma_chan_read(c, CSR); in omap_dma_clear_csr()
388 omap_dma_chan_write(c, CSR, ~0); in omap_dma_clear_csr()
393 unsigned val = omap_dma_chan_read(c, CSR); in omap_dma_get_csr()
396 omap_dma_chan_write(c, CSR, val); in omap_dma_get_csr()
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| /linux/drivers/misc/eeprom/ |
| A D | Kconfig | 113 tristate "IDT 89HPESx PCIe-swtiches EEPROM / CSR support"
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| /linux/arch/arm/mach-tegra/ |
| A D | sleep-tegra30.S | 233 ldr r3, [r1] @ read CSR
234 str r3, [r1] @ clear CSR
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| /linux/drivers/net/ethernet/renesas/ |
| A D | ravb.h | 52 CSR = 0x000C, enumerator
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| /linux/Documentation/devicetree/bindings/net/ |
| A D | snps,dwc-qos-ethernet.txt | 43 The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
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| /linux/drivers/spi/ |
| A D | spi-at91-usart.c | 294 aus->status = at91_usart_spi_readl(aus, CSR); in at91_usart_spi_read_status()
|