Searched refs:CTR (Results 1 – 17 of 17) sorted by relevance
| /linux/arch/x86/crypto/ |
| A D | aesni-intel_avx-x86_64.S | 1002 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1080 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1084 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1088 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1092 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1096 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1100 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1104 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1108 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1950 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
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| A D | aesni-intel_asm.S | 142 #define CTR %xmm11 macro
2723 movaps IV, CTR
2724 pshufb BSWAP_MASK, CTR
2727 movq CTR, TCTR_LOW
2747 paddq INC, CTR
2751 paddq INC, CTR
2754 movaps CTR, IV
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| /linux/tools/perf/arch/powerpc/tests/ |
| A D | regs_load.S | 38 #define CTR 35 * 8 macro
90 std 4, CTR(3)
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| /linux/arch/arm64/crypto/ |
| A D | Kconfig | 87 tristate "AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions"
93 tristate "AES in ECB/CBC/CTR/XTS modes using NEON instructions"
117 tristate "AES in ECB/CBC/CTR/XTS modes using bit-sliced NEON algorithm"
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| /linux/Documentation/crypto/ |
| A D | architecture.rst | 265 the AES-NI implementation, the CTR mode, the GHASH implementation and
332 During instantiation of the GCM handle, the CTR(AES) and GHASH
333 ciphers are instantiated. The cipher handles for CTR(AES) and GHASH
336 The GCM implementation is responsible to invoke the CTR mode AES and
341 with the instantiated CTR(AES) cipher handle.
343 During instantiation of the CTR(AES) cipher, the CIPHER type
347 That means that the SKCIPHER implementation of CTR(AES) only
348 implements the CTR block chaining mode. After performing the block
351 4. The SKCIPHER of CTR(AES) now invokes the CIPHER API with the AES
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| /linux/arch/arm/crypto/ |
| A D | Kconfig | 108 CTR and XTS modes
110 Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
123 Use an implementation of AES in CBC, CTR and XTS modes that uses
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| A D | aes-ce-core.S | 449 vst1.8 {q7}, [r5] @ return next CTR value
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| /linux/Documentation/devicetree/bindings/crypto/ |
| A D | samsung-slimsss.yaml | 15 -- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
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| /linux/drivers/crypto/ux500/ |
| A D | Kconfig | 15 AES-ECB, CBC and CTR with keys sizes of 128, 192 and 256 bit sizes.
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| /linux/drivers/platform/x86/intel/telemetry/ |
| A D | debugfs.c | 76 #define TELEM_CHECK_AND_PARSE_CTRS(EVTID, CTR) { \ argument
78 (CTR) = evtlog[index].telem_evtlog; \
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| /linux/crypto/ |
| A D | Kconfig | 360 xoring it with a salt. This algorithm is mainly useful for CTR
392 tristate "CTR support"
396 CTR: Counter mode
1073 and GCM drivers, and other CTR or CMAC/XCBC based modes that rely
1114 acceleration for CTR.
1149 for popular block cipher modes ECB, CBC, CTR and XTS is supported.
1824 bool "Enable CTR DRBG"
1828 Enable the CTR DRBG variant as defined in NIST SP800-90A.
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| /linux/drivers/crypto/ |
| A D | Kconfig | 197 As of z196 the CTR mode is hardware accelerated.
212 As of z196 the CTR mode is hardware accelerated for all AES
685 - AES (CBC, CTR, ECB, XTS)
696 - AES (CBC, CTR, ECB, XTS)
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| /linux/arch/powerpc/platforms/8xx/ |
| A D | Kconfig | 120 (by not placing conditional branches or branches to LR or CTR
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| /linux/Documentation/powerpc/ |
| A D | papr_hcalls.rst | 84 | CTR | Y | Loop Counter |
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| A D | transactional_memory.rst | 63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
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| /linux/drivers/platform/x86/ |
| A D | sony-laptop.c | 711 SNC_HANDLE(CTR, snc_CTR_get, snc_CTR_set, NULL, 1),
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| /linux/ |
| A D | modules.builtin.modinfo | 1 …to-ecb(aes)�aes_glue_ce.alias=ecb(aes)�aes_glue_ce.description=AES-ECB/CBC/CTR/XTS using ARMv8 Cry…
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