Searched refs:CTRL1 (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/net/ethernet/intel/ixgb/ |
| A D | ixgb_hw.c | 82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); in ixgb_mac_reset()
292 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); in ixgb_init_hw()
294 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); in ixgb_init_hw()
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| A D | ixgb_ethtool.c | 218 *reg++ = IXGB_READ_REG(hw, CTRL1); /* 1 */ in ixgb_get_regs()
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| /linux/drivers/regulator/ |
| A D | max77802-regulator.c | 381 .enable_reg = MAX77802_REG_BUCK ## num ## CTRL1, \
384 .ramp_reg = MAX77802_REG_BUCK ## num ## CTRL1, \
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| /linux/sound/soc/codecs/ |
| A D | ak4613.c | 27 #define CTRL1 0x03 /* Control 1 */ macro
433 snd_soc_component_update_bits(component, CTRL1, FMT_MASK, fmt_ctrl); in ak4613_dai_hw_params()
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| /linux/drivers/net/ethernet/amd/ |
| A D | amd8111e.h | 51 #define CTRL1 0x6C /* Control1 register */ macro
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| A D | amd8111e.c | 441 reg_val = readl(mmio + CTRL1); in amd8111e_restart()
443 writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1); in amd8111e_restart()
580 writel(CTRL1_DEFAULT, mmio + CTRL1); in amd8111e_init_hw_default()
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| /linux/Documentation/devicetree/bindings/mfd/ |
| A D | samsung,s2mps11.yaml | 48 the PMIC must manually set PWRHOLD bit in CTRL1 register to turn off the
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| /linux/drivers/media/i2c/ |
| A D | ov2640.c | 98 #define CTRL1 0xC3 /* DSP Module enable 1 */ macro
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