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Searched refs:ChlWidth (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/staging/rtl8192e/
A Drtl819x_HTProc.c299 pCapELE->ChlWidth = 0; in HTConstructCapabilityElement()
301 pCapELE->ChlWidth = (pHT->bRegBW40MHz ? 1 : 0); in HTConstructCapabilityElement()
318 pCapELE->ChlWidth, pCapELE->MaxAMSDUSize, pCapELE->DssCCk); in HTConstructCapabilityElement()
348 pCapELE->ChlWidth = 0; in HTConstructCapabilityElement()
544 HTSetConnectBwMode(ieee, (enum ht_channel_width)(pPeerHTCap->ChlWidth), in HTOnAssocRsp()
A Drtl819x_HT.h29 u8 ChlWidth:1; member
A Drtllib_wx.c149 is40M = (ht_cap->ChlWidth) ? 1 : 0; in rtl819x_translate_scan()
150 isShortGI = (ht_cap->ChlWidth) ? in rtl819x_translate_scan()
A Drtllib_rx.c2013 (ht->bd_ht_cap_buf))->ChlWidth); in rtllib_parse_mfie_ht_cap()
/linux/drivers/staging/rtl8192u/ieee80211/
A Drtl819x_HTProc.c141 …IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupported Channel Width = %s\n", (pCapELE->ChlWidth) ? "20MHz… in HTDebugHTCapability()
494 pCapELE->ChlWidth = 0; in HTConstructCapabilityElement()
496 pCapELE->ChlWidth = (pHT->bRegBW40MHz ? 1 : 0); in HTConstructCapabilityElement()
517 …DL_HT, "TX HT cap/info ele BW=%d MaxAMSDUSize:%d DssCCk:%d\n", pCapELE->ChlWidth, pCapELE->MaxAMSD… in HTConstructCapabilityElement()
877 …HTSetConnectBwMode(ieee, (enum ht_channel_width)(pPeerHTCap->ChlWidth), (enum ht_extension_chan_of… in HTOnAssocRsp()
A Drtl819x_HT.h43 u8 ChlWidth:1; member
A Dieee80211_wx.c141 is40M = (ht_cap->ChlWidth) ? 1 : 0; in rtl819x_translate_scan()
142 isShortGI = (ht_cap->ChlWidth) ? in rtl819x_translate_scan()

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