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Searched refs:DCACHE_WAY_SIZE (Results 1 – 11 of 11) sorted by relevance

/linux/arch/xtensa/include/asm/
A Dcache.h20 #define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) macro
26 #if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
27 # define CACHE_WAY_SIZE DCACHE_WAY_SIZE
A Dshmparam.h19 #define SHMLBA ((PAGE_SIZE > DCACHE_WAY_SIZE)? PAGE_SIZE : DCACHE_WAY_SIZE)
A Dcacheflush.h69 #if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
95 ((DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP))
163 #if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
A Dpgtable.h72 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
73 #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
74 #define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
179 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
310 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK in update_pte()
A Dpage.h66 #if DCACHE_WAY_SIZE > PAGE_SIZE
68 # define DCACHE_ALIAS_MASK (PAGE_MASK & (DCACHE_WAY_SIZE - 1))
140 #if defined(CONFIG_MMU) && DCACHE_WAY_SIZE > PAGE_SIZE
A Dhighmem.h30 #if DCACHE_WAY_SIZE > PAGE_SIZE
/linux/Documentation/xtensa/
A Dmmu.rst86 | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE
89 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
129 | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE
132 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
173 | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE
176 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
/linux/arch/xtensa/mm/
A Dcache.c58 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
225 #if (DCACHE_WAY_SIZE > PAGE_SIZE) in update_mmu_cache()
258 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
A Dhighmem.c15 #if DCACHE_WAY_SIZE > PAGE_SIZE
A Dmisc.S110 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
216 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
/linux/arch/xtensa/kernel/
A Dentry.S1725 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
1856 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK

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