Searched refs:DCCG_GATE_DISABLE_CNTL3 (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_dccg.c | 124 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_dpstreamclk()
133 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_dpstreamclk()
183 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
191 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
199 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
207 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
232 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_symclk32_se()
240 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_symclk32_se()
248 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_symclk32_se()
256 REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_symclk32_se()
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| A D | dcn31_dccg.h | 69 SR(DCCG_GATE_DISABLE_CNTL3),\
138 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\
139 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\
140 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
141 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
142 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
143 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
144 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
145 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dccg.h | 236 uint32_t DCCG_GATE_DISABLE_CNTL3; member
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