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Searched refs:DCLK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/inc/
A Dpower_state.h144 uint32_t DCLK; member
/linux/drivers/gpu/drm/i915/gt/
A Dintel_llc.c62 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; in get_ia_constants()
/linux/Documentation/devicetree/bindings/clock/
A Dst,nomadik.txt99 58: 3DCLK
/linux/arch/arm/boot/dts/
A Dimx6dl-eckelmann-ci4x10.dts220 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dprocesspptables.c759 ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK); in init_non_clock_fields()
762 ps->uvd_clocks.DCLK = 0; in init_non_clock_fields()
A Dsmu10_hwmgr.c924 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu10_dpm_get_pp_table_entry()
A Dsmu8_hwmgr.c1416 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
A Dsmu7_hwmgr.c3597 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3690 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v1()
3838 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v0()
A Dvega10_hwmgr.c3144 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()
3224 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c113 CLK_MAP(DCLK, CLOCK_DCLK),
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Daldebaran_ppt.c147 CLK_MAP(DCLK, PPCLK_DCLK),
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Darcturus_ppt.c173 CLK_MAP(DCLK, PPCLK_DCLK),
A Dnavi10_ppt.c157 CLK_MAP(DCLK, PPCLK_DCLK),
A Dsienna_cichlid_ppt.c157 CLK_MAP(DCLK, PPCLK_DCLK_0),
/linux/drivers/gpu/drm/i915/
A Di915_reg.h3844 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) macro

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