1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA_QM_0_MASKS_H_ 14 #define ASIC_REG_DMA_QM_0_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DMA_QM_0 (Prototype: QMAN) 19 ***************************************** 20 */ 21 22 /* DMA_QM_0_GLBL_CFG0 */ 23 #define DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT 0 24 #define DMA_QM_0_GLBL_CFG0_PQF_EN_MASK 0x1 25 #define DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT 1 26 #define DMA_QM_0_GLBL_CFG0_CQF_EN_MASK 0x2 27 #define DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT 2 28 #define DMA_QM_0_GLBL_CFG0_CP_EN_MASK 0x4 29 #define DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT 3 30 #define DMA_QM_0_GLBL_CFG0_DMA_EN_MASK 0x8 31 32 /* DMA_QM_0_GLBL_CFG1 */ 33 #define DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT 0 34 #define DMA_QM_0_GLBL_CFG1_PQF_STOP_MASK 0x1 35 #define DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT 1 36 #define DMA_QM_0_GLBL_CFG1_CQF_STOP_MASK 0x2 37 #define DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT 2 38 #define DMA_QM_0_GLBL_CFG1_CP_STOP_MASK 0x4 39 #define DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT 3 40 #define DMA_QM_0_GLBL_CFG1_DMA_STOP_MASK 0x8 41 #define DMA_QM_0_GLBL_CFG1_PQF_FLUSH_SHIFT 8 42 #define DMA_QM_0_GLBL_CFG1_PQF_FLUSH_MASK 0x100 43 #define DMA_QM_0_GLBL_CFG1_CQF_FLUSH_SHIFT 9 44 #define DMA_QM_0_GLBL_CFG1_CQF_FLUSH_MASK 0x200 45 #define DMA_QM_0_GLBL_CFG1_CP_FLUSH_SHIFT 10 46 #define DMA_QM_0_GLBL_CFG1_CP_FLUSH_MASK 0x400 47 #define DMA_QM_0_GLBL_CFG1_DMA_FLUSH_SHIFT 11 48 #define DMA_QM_0_GLBL_CFG1_DMA_FLUSH_MASK 0x800 49 50 /* DMA_QM_0_GLBL_PROT */ 51 #define DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT 0 52 #define DMA_QM_0_GLBL_PROT_PQF_PROT_MASK 0x1 53 #define DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT 1 54 #define DMA_QM_0_GLBL_PROT_CQF_PROT_MASK 0x2 55 #define DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT 2 56 #define DMA_QM_0_GLBL_PROT_CP_PROT_MASK 0x4 57 #define DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT 3 58 #define DMA_QM_0_GLBL_PROT_DMA_PROT_MASK 0x8 59 #define DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 60 #define DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 61 #define DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 62 #define DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 63 #define DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT 6 64 #define DMA_QM_0_GLBL_PROT_CP_ERR_PROT_MASK 0x40 65 #define DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 66 #define DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 67 68 /* DMA_QM_0_GLBL_ERR_CFG */ 69 #define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 70 #define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 71 #define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 72 #define DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 73 #define DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 74 #define DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 75 #define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 76 #define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 77 #define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 78 #define DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 79 #define DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 80 #define DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 81 #define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 82 #define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 83 #define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 84 #define DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 85 #define DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 86 #define DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 87 #define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 88 #define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 89 #define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 90 #define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 91 #define DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 92 #define DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 93 94 /* DMA_QM_0_GLBL_ERR_ADDR_LO */ 95 #define DMA_QM_0_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 96 #define DMA_QM_0_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF 97 98 /* DMA_QM_0_GLBL_ERR_ADDR_HI */ 99 #define DMA_QM_0_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 100 #define DMA_QM_0_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF 101 102 /* DMA_QM_0_GLBL_ERR_WDATA */ 103 #define DMA_QM_0_GLBL_ERR_WDATA_VAL_SHIFT 0 104 #define DMA_QM_0_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF 105 106 /* DMA_QM_0_GLBL_SECURE_PROPS */ 107 #define DMA_QM_0_GLBL_SECURE_PROPS_ASID_SHIFT 0 108 #define DMA_QM_0_GLBL_SECURE_PROPS_ASID_MASK 0x3FF 109 #define DMA_QM_0_GLBL_SECURE_PROPS_MMBP_SHIFT 10 110 #define DMA_QM_0_GLBL_SECURE_PROPS_MMBP_MASK 0x400 111 112 /* DMA_QM_0_GLBL_NON_SECURE_PROPS */ 113 #define DMA_QM_0_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 114 #define DMA_QM_0_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF 115 #define DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 116 #define DMA_QM_0_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 117 118 /* DMA_QM_0_GLBL_STS0 */ 119 #define DMA_QM_0_GLBL_STS0_PQF_IDLE_SHIFT 0 120 #define DMA_QM_0_GLBL_STS0_PQF_IDLE_MASK 0x1 121 #define DMA_QM_0_GLBL_STS0_CQF_IDLE_SHIFT 1 122 #define DMA_QM_0_GLBL_STS0_CQF_IDLE_MASK 0x2 123 #define DMA_QM_0_GLBL_STS0_CP_IDLE_SHIFT 2 124 #define DMA_QM_0_GLBL_STS0_CP_IDLE_MASK 0x4 125 #define DMA_QM_0_GLBL_STS0_DMA_IDLE_SHIFT 3 126 #define DMA_QM_0_GLBL_STS0_DMA_IDLE_MASK 0x8 127 #define DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT 4 128 #define DMA_QM_0_GLBL_STS0_PQF_IS_STOP_MASK 0x10 129 #define DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT 5 130 #define DMA_QM_0_GLBL_STS0_CQF_IS_STOP_MASK 0x20 131 #define DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT 6 132 #define DMA_QM_0_GLBL_STS0_CP_IS_STOP_MASK 0x40 133 #define DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT 7 134 #define DMA_QM_0_GLBL_STS0_DMA_IS_STOP_MASK 0x80 135 136 /* DMA_QM_0_GLBL_STS1 */ 137 #define DMA_QM_0_GLBL_STS1_PQF_RD_ERR_SHIFT 0 138 #define DMA_QM_0_GLBL_STS1_PQF_RD_ERR_MASK 0x1 139 #define DMA_QM_0_GLBL_STS1_CQF_RD_ERR_SHIFT 1 140 #define DMA_QM_0_GLBL_STS1_CQF_RD_ERR_MASK 0x2 141 #define DMA_QM_0_GLBL_STS1_CP_RD_ERR_SHIFT 2 142 #define DMA_QM_0_GLBL_STS1_CP_RD_ERR_MASK 0x4 143 #define DMA_QM_0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 144 #define DMA_QM_0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 145 #define DMA_QM_0_GLBL_STS1_CP_STOP_OP_SHIFT 4 146 #define DMA_QM_0_GLBL_STS1_CP_STOP_OP_MASK 0x10 147 #define DMA_QM_0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 148 #define DMA_QM_0_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 149 #define DMA_QM_0_GLBL_STS1_DMA_RD_ERR_SHIFT 8 150 #define DMA_QM_0_GLBL_STS1_DMA_RD_ERR_MASK 0x100 151 #define DMA_QM_0_GLBL_STS1_DMA_WR_ERR_SHIFT 9 152 #define DMA_QM_0_GLBL_STS1_DMA_WR_ERR_MASK 0x200 153 #define DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 154 #define DMA_QM_0_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 155 #define DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 156 #define DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 157 158 /* DMA_QM_0_PQ_BASE_LO */ 159 #define DMA_QM_0_PQ_BASE_LO_VAL_SHIFT 0 160 #define DMA_QM_0_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF 161 162 /* DMA_QM_0_PQ_BASE_HI */ 163 #define DMA_QM_0_PQ_BASE_HI_VAL_SHIFT 0 164 #define DMA_QM_0_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF 165 166 /* DMA_QM_0_PQ_SIZE */ 167 #define DMA_QM_0_PQ_SIZE_VAL_SHIFT 0 168 #define DMA_QM_0_PQ_SIZE_VAL_MASK 0xFFFFFFFF 169 170 /* DMA_QM_0_PQ_PI */ 171 #define DMA_QM_0_PQ_PI_VAL_SHIFT 0 172 #define DMA_QM_0_PQ_PI_VAL_MASK 0xFFFFFFFF 173 174 /* DMA_QM_0_PQ_CI */ 175 #define DMA_QM_0_PQ_CI_VAL_SHIFT 0 176 #define DMA_QM_0_PQ_CI_VAL_MASK 0xFFFFFFFF 177 178 /* DMA_QM_0_PQ_CFG0 */ 179 #define DMA_QM_0_PQ_CFG0_RESERVED_SHIFT 0 180 #define DMA_QM_0_PQ_CFG0_RESERVED_MASK 0x1 181 182 /* DMA_QM_0_PQ_CFG1 */ 183 #define DMA_QM_0_PQ_CFG1_CREDIT_LIM_SHIFT 0 184 #define DMA_QM_0_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF 185 #define DMA_QM_0_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 186 #define DMA_QM_0_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 187 188 /* DMA_QM_0_PQ_ARUSER */ 189 #define DMA_QM_0_PQ_ARUSER_NOSNOOP_SHIFT 0 190 #define DMA_QM_0_PQ_ARUSER_NOSNOOP_MASK 0x1 191 #define DMA_QM_0_PQ_ARUSER_WORD_SHIFT 1 192 #define DMA_QM_0_PQ_ARUSER_WORD_MASK 0x2 193 194 /* DMA_QM_0_PQ_PUSH0 */ 195 #define DMA_QM_0_PQ_PUSH0_PTR_LO_SHIFT 0 196 #define DMA_QM_0_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF 197 198 /* DMA_QM_0_PQ_PUSH1 */ 199 #define DMA_QM_0_PQ_PUSH1_PTR_HI_SHIFT 0 200 #define DMA_QM_0_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF 201 202 /* DMA_QM_0_PQ_PUSH2 */ 203 #define DMA_QM_0_PQ_PUSH2_TSIZE_SHIFT 0 204 #define DMA_QM_0_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF 205 206 /* DMA_QM_0_PQ_PUSH3 */ 207 #define DMA_QM_0_PQ_PUSH3_RPT_SHIFT 0 208 #define DMA_QM_0_PQ_PUSH3_RPT_MASK 0xFFFF 209 #define DMA_QM_0_PQ_PUSH3_CTL_SHIFT 16 210 #define DMA_QM_0_PQ_PUSH3_CTL_MASK 0xFFFF0000 211 212 /* DMA_QM_0_PQ_STS0 */ 213 #define DMA_QM_0_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 214 #define DMA_QM_0_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF 215 #define DMA_QM_0_PQ_STS0_PQ_FREE_CNT_SHIFT 16 216 #define DMA_QM_0_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 217 218 /* DMA_QM_0_PQ_STS1 */ 219 #define DMA_QM_0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 220 #define DMA_QM_0_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF 221 #define DMA_QM_0_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 222 #define DMA_QM_0_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 223 #define DMA_QM_0_PQ_STS1_PQ_BUSY_SHIFT 31 224 #define DMA_QM_0_PQ_STS1_PQ_BUSY_MASK 0x80000000 225 226 /* DMA_QM_0_PQ_RD_RATE_LIM_EN */ 227 #define DMA_QM_0_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 228 #define DMA_QM_0_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 229 230 /* DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN */ 231 #define DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 232 #define DMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF 233 234 /* DMA_QM_0_PQ_RD_RATE_LIM_SAT */ 235 #define DMA_QM_0_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 236 #define DMA_QM_0_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF 237 238 /* DMA_QM_0_PQ_RD_RATE_LIM_TOUT */ 239 #define DMA_QM_0_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 240 #define DMA_QM_0_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF 241 242 /* DMA_QM_0_CQ_CFG0 */ 243 #define DMA_QM_0_CQ_CFG0_RESERVED_SHIFT 0 244 #define DMA_QM_0_CQ_CFG0_RESERVED_MASK 0x1 245 246 /* DMA_QM_0_CQ_CFG1 */ 247 #define DMA_QM_0_CQ_CFG1_CREDIT_LIM_SHIFT 0 248 #define DMA_QM_0_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF 249 #define DMA_QM_0_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 250 #define DMA_QM_0_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 251 252 /* DMA_QM_0_CQ_ARUSER */ 253 #define DMA_QM_0_CQ_ARUSER_NOSNOOP_SHIFT 0 254 #define DMA_QM_0_CQ_ARUSER_NOSNOOP_MASK 0x1 255 #define DMA_QM_0_CQ_ARUSER_WORD_SHIFT 1 256 #define DMA_QM_0_CQ_ARUSER_WORD_MASK 0x2 257 258 /* DMA_QM_0_CQ_PTR_LO */ 259 #define DMA_QM_0_CQ_PTR_LO_VAL_SHIFT 0 260 #define DMA_QM_0_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF 261 262 /* DMA_QM_0_CQ_PTR_HI */ 263 #define DMA_QM_0_CQ_PTR_HI_VAL_SHIFT 0 264 #define DMA_QM_0_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF 265 266 /* DMA_QM_0_CQ_TSIZE */ 267 #define DMA_QM_0_CQ_TSIZE_VAL_SHIFT 0 268 #define DMA_QM_0_CQ_TSIZE_VAL_MASK 0xFFFFFFFF 269 270 /* DMA_QM_0_CQ_CTL */ 271 #define DMA_QM_0_CQ_CTL_RPT_SHIFT 0 272 #define DMA_QM_0_CQ_CTL_RPT_MASK 0xFFFF 273 #define DMA_QM_0_CQ_CTL_CTL_SHIFT 16 274 #define DMA_QM_0_CQ_CTL_CTL_MASK 0xFFFF0000 275 276 /* DMA_QM_0_CQ_PTR_LO_STS */ 277 #define DMA_QM_0_CQ_PTR_LO_STS_VAL_SHIFT 0 278 #define DMA_QM_0_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF 279 280 /* DMA_QM_0_CQ_PTR_HI_STS */ 281 #define DMA_QM_0_CQ_PTR_HI_STS_VAL_SHIFT 0 282 #define DMA_QM_0_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF 283 284 /* DMA_QM_0_CQ_TSIZE_STS */ 285 #define DMA_QM_0_CQ_TSIZE_STS_VAL_SHIFT 0 286 #define DMA_QM_0_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF 287 288 /* DMA_QM_0_CQ_CTL_STS */ 289 #define DMA_QM_0_CQ_CTL_STS_RPT_SHIFT 0 290 #define DMA_QM_0_CQ_CTL_STS_RPT_MASK 0xFFFF 291 #define DMA_QM_0_CQ_CTL_STS_CTL_SHIFT 16 292 #define DMA_QM_0_CQ_CTL_STS_CTL_MASK 0xFFFF0000 293 294 /* DMA_QM_0_CQ_STS0 */ 295 #define DMA_QM_0_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 296 #define DMA_QM_0_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF 297 #define DMA_QM_0_CQ_STS0_CQ_FREE_CNT_SHIFT 16 298 #define DMA_QM_0_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 299 300 /* DMA_QM_0_CQ_STS1 */ 301 #define DMA_QM_0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 302 #define DMA_QM_0_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF 303 #define DMA_QM_0_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 304 #define DMA_QM_0_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 305 #define DMA_QM_0_CQ_STS1_CQ_BUSY_SHIFT 31 306 #define DMA_QM_0_CQ_STS1_CQ_BUSY_MASK 0x80000000 307 308 /* DMA_QM_0_CQ_RD_RATE_LIM_EN */ 309 #define DMA_QM_0_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 310 #define DMA_QM_0_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 311 312 /* DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN */ 313 #define DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 314 #define DMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF 315 316 /* DMA_QM_0_CQ_RD_RATE_LIM_SAT */ 317 #define DMA_QM_0_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 318 #define DMA_QM_0_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF 319 320 /* DMA_QM_0_CQ_RD_RATE_LIM_TOUT */ 321 #define DMA_QM_0_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 322 #define DMA_QM_0_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF 323 324 /* DMA_QM_0_CQ_IFIFO_CNT */ 325 #define DMA_QM_0_CQ_IFIFO_CNT_VAL_SHIFT 0 326 #define DMA_QM_0_CQ_IFIFO_CNT_VAL_MASK 0x3 327 328 /* DMA_QM_0_CP_MSG_BASE0_ADDR_LO */ 329 #define DMA_QM_0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 330 #define DMA_QM_0_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF 331 332 /* DMA_QM_0_CP_MSG_BASE0_ADDR_HI */ 333 #define DMA_QM_0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 334 #define DMA_QM_0_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF 335 336 /* DMA_QM_0_CP_MSG_BASE1_ADDR_LO */ 337 #define DMA_QM_0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 338 #define DMA_QM_0_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF 339 340 /* DMA_QM_0_CP_MSG_BASE1_ADDR_HI */ 341 #define DMA_QM_0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 342 #define DMA_QM_0_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF 343 344 /* DMA_QM_0_CP_MSG_BASE2_ADDR_LO */ 345 #define DMA_QM_0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 346 #define DMA_QM_0_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF 347 348 /* DMA_QM_0_CP_MSG_BASE2_ADDR_HI */ 349 #define DMA_QM_0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 350 #define DMA_QM_0_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF 351 352 /* DMA_QM_0_CP_MSG_BASE3_ADDR_LO */ 353 #define DMA_QM_0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 354 #define DMA_QM_0_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF 355 356 /* DMA_QM_0_CP_MSG_BASE3_ADDR_HI */ 357 #define DMA_QM_0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 358 #define DMA_QM_0_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF 359 360 /* DMA_QM_0_CP_LDMA_TSIZE_OFFSET */ 361 #define DMA_QM_0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 362 #define DMA_QM_0_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF 363 364 /* DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET */ 365 #define DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 366 #define DMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF 367 368 /* DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET */ 369 #define DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 370 #define DMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF 371 372 /* DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET */ 373 #define DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 374 #define DMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF 375 376 /* DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET */ 377 #define DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 378 #define DMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF 379 380 /* DMA_QM_0_CP_LDMA_COMMIT_OFFSET */ 381 #define DMA_QM_0_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 382 #define DMA_QM_0_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF 383 384 /* DMA_QM_0_CP_FENCE0_RDATA */ 385 #define DMA_QM_0_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 386 #define DMA_QM_0_CP_FENCE0_RDATA_INC_VAL_MASK 0xF 387 388 /* DMA_QM_0_CP_FENCE1_RDATA */ 389 #define DMA_QM_0_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 390 #define DMA_QM_0_CP_FENCE1_RDATA_INC_VAL_MASK 0xF 391 392 /* DMA_QM_0_CP_FENCE2_RDATA */ 393 #define DMA_QM_0_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 394 #define DMA_QM_0_CP_FENCE2_RDATA_INC_VAL_MASK 0xF 395 396 /* DMA_QM_0_CP_FENCE3_RDATA */ 397 #define DMA_QM_0_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 398 #define DMA_QM_0_CP_FENCE3_RDATA_INC_VAL_MASK 0xF 399 400 /* DMA_QM_0_CP_FENCE0_CNT */ 401 #define DMA_QM_0_CP_FENCE0_CNT_VAL_SHIFT 0 402 #define DMA_QM_0_CP_FENCE0_CNT_VAL_MASK 0xFF 403 404 /* DMA_QM_0_CP_FENCE1_CNT */ 405 #define DMA_QM_0_CP_FENCE1_CNT_VAL_SHIFT 0 406 #define DMA_QM_0_CP_FENCE1_CNT_VAL_MASK 0xFF 407 408 /* DMA_QM_0_CP_FENCE2_CNT */ 409 #define DMA_QM_0_CP_FENCE2_CNT_VAL_SHIFT 0 410 #define DMA_QM_0_CP_FENCE2_CNT_VAL_MASK 0xFF 411 412 /* DMA_QM_0_CP_FENCE3_CNT */ 413 #define DMA_QM_0_CP_FENCE3_CNT_VAL_SHIFT 0 414 #define DMA_QM_0_CP_FENCE3_CNT_VAL_MASK 0xFF 415 416 /* DMA_QM_0_CP_STS */ 417 #define DMA_QM_0_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 418 #define DMA_QM_0_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF 419 #define DMA_QM_0_CP_STS_ERDY_SHIFT 16 420 #define DMA_QM_0_CP_STS_ERDY_MASK 0x10000 421 #define DMA_QM_0_CP_STS_RRDY_SHIFT 17 422 #define DMA_QM_0_CP_STS_RRDY_MASK 0x20000 423 #define DMA_QM_0_CP_STS_MRDY_SHIFT 18 424 #define DMA_QM_0_CP_STS_MRDY_MASK 0x40000 425 #define DMA_QM_0_CP_STS_SW_STOP_SHIFT 19 426 #define DMA_QM_0_CP_STS_SW_STOP_MASK 0x80000 427 #define DMA_QM_0_CP_STS_FENCE_ID_SHIFT 20 428 #define DMA_QM_0_CP_STS_FENCE_ID_MASK 0x300000 429 #define DMA_QM_0_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 430 #define DMA_QM_0_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 431 432 /* DMA_QM_0_CP_CURRENT_INST_LO */ 433 #define DMA_QM_0_CP_CURRENT_INST_LO_VAL_SHIFT 0 434 #define DMA_QM_0_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF 435 436 /* DMA_QM_0_CP_CURRENT_INST_HI */ 437 #define DMA_QM_0_CP_CURRENT_INST_HI_VAL_SHIFT 0 438 #define DMA_QM_0_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF 439 440 /* DMA_QM_0_CP_BARRIER_CFG */ 441 #define DMA_QM_0_CP_BARRIER_CFG_EBGUARD_SHIFT 0 442 #define DMA_QM_0_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF 443 444 /* DMA_QM_0_CP_DBG_0 */ 445 #define DMA_QM_0_CP_DBG_0_VAL_SHIFT 0 446 #define DMA_QM_0_CP_DBG_0_VAL_MASK 0xFF 447 448 /* DMA_QM_0_PQ_BUF_ADDR */ 449 #define DMA_QM_0_PQ_BUF_ADDR_VAL_SHIFT 0 450 #define DMA_QM_0_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF 451 452 /* DMA_QM_0_PQ_BUF_RDATA */ 453 #define DMA_QM_0_PQ_BUF_RDATA_VAL_SHIFT 0 454 #define DMA_QM_0_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF 455 456 /* DMA_QM_0_CQ_BUF_ADDR */ 457 #define DMA_QM_0_CQ_BUF_ADDR_VAL_SHIFT 0 458 #define DMA_QM_0_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF 459 460 /* DMA_QM_0_CQ_BUF_RDATA */ 461 #define DMA_QM_0_CQ_BUF_RDATA_VAL_SHIFT 0 462 #define DMA_QM_0_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF 463 464 #endif /* ASIC_REG_DMA_QM_0_MASKS_H_ */ 465