Searched refs:DPLL_FPA01_P1_POST_DIV_SHIFT (Results 1 – 6 of 6) sorted by relevance
338 DPLL_FPA01_P1_POST_DIV_SHIFT); in psb_intel_crtc_clock_get()354 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in psb_intel_crtc_clock_get()
869 DPLL_FPA01_P1_POST_DIV_SHIFT); in cdv_intel_crtc_clock_get()889 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in cdv_intel_crtc_clock_get()
254 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
836 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()842 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()896 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()901 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()1044 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
5816 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()5847 DPLL_FPA01_P1_POST_DIV_SHIFT); in i9xx_crtc_clock_get()5858 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in i9xx_crtc_clock_get()11133 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | in i830_enable_pipe()
3566 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
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