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Searched refs:DPU_MAX_PLANES (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_util.h111 u32 preload_x[DPU_MAX_PLANES];
112 u32 preload_y[DPU_MAX_PLANES];
113 u32 src_width[DPU_MAX_PLANES];
114 u32 src_height[DPU_MAX_PLANES];
171 int32_t left_ftch[DPU_MAX_PLANES];
173 int32_t top_ftch[DPU_MAX_PLANES];
174 int32_t btm_ftch[DPU_MAX_PLANES];
179 int32_t left_rpt[DPU_MAX_PLANES];
180 int32_t right_rpt[DPU_MAX_PLANES];
181 int32_t top_rpt[DPU_MAX_PLANES];
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A Ddpu_hw_sspp.h105 int init_phase_x[DPU_MAX_PLANES];
124 int left_ftch[DPU_MAX_PLANES];
125 int right_ftch[DPU_MAX_PLANES];
126 int top_ftch[DPU_MAX_PLANES];
127 int btm_ftch[DPU_MAX_PLANES];
133 int left_rpt[DPU_MAX_PLANES];
134 int right_rpt[DPU_MAX_PLANES];
135 int top_rpt[DPU_MAX_PLANES];
136 int btm_rpt[DPU_MAX_PLANES];
138 uint32_t roi_w[DPU_MAX_PLANES];
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A Ddpu_hw_mdss.h29 #ifndef DPU_MAX_PLANES
30 #define DPU_MAX_PLANES 4 macro
365 u8 element[DPU_MAX_PLANES];
366 u8 bits[DPU_MAX_PLANES];
398 uint32_t plane_addr[DPU_MAX_PLANES];
399 uint32_t plane_size[DPU_MAX_PLANES];
400 uint32_t plane_pitch[DPU_MAX_PLANES];
A Ddpu_formats.c671 for (i = 0; i < DPU_MAX_PLANES; i++) in _dpu_format_get_plane_sizes_ubwc()
738 for (i = 0; i < layout->num_planes && i < DPU_MAX_PLANES; ++i) { in _dpu_format_get_plane_sizes_linear()
743 for (i = 0; i < DPU_MAX_PLANES; i++) in _dpu_format_get_plane_sizes_linear()
898 uint32_t plane_addr[DPU_MAX_PLANES]; in dpu_format_populate_layout()
920 for (i = 0; i < DPU_MAX_PLANES; ++i) in dpu_format_populate_layout()
A Ddpu_hw_sspp.c372 for (color = 0; color < DPU_MAX_PLANES; color++) { in dpu_hw_sspp_setup_pe_config()
A Ddpu_plane.c573 for (i = 0; i < DPU_MAX_PLANES; i++) { in _dpu_plane_setup_scaler3()

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