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Searched refs:DPU_REG_WRITE (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_util.c158 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3_lut()
210 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3lite_lut()
386 DPU_REG_WRITE(c, csc_reg_off, val); in dpu_hw_csc_setup()
389 DPU_REG_WRITE(c, csc_reg_off + 0x4, val); in dpu_hw_csc_setup()
392 DPU_REG_WRITE(c, csc_reg_off + 0x8, val); in dpu_hw_csc_setup()
395 DPU_REG_WRITE(c, csc_reg_off + 0xc, val); in dpu_hw_csc_setup()
397 DPU_REG_WRITE(c, csc_reg_off + 0x10, val); in dpu_hw_csc_setup()
401 DPU_REG_WRITE(c, csc_reg_off + 0x14, val); in dpu_hw_csc_setup()
403 DPU_REG_WRITE(c, csc_reg_off + 0x18, val); in dpu_hw_csc_setup()
405 DPU_REG_WRITE(c, csc_reg_off + 0x1c, val); in dpu_hw_csc_setup()
[all …]
A Ddpu_hw_intf.c186 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); in dpu_hw_intf_setup_timing_engine()
190 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); in dpu_hw_intf_setup_timing_engine()
192 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, in dpu_hw_intf_setup_timing_engine()
194 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); in dpu_hw_intf_setup_timing_engine()
197 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); in dpu_hw_intf_setup_timing_engine()
202 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); in dpu_hw_intf_setup_timing_engine()
204 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); in dpu_hw_intf_setup_timing_engine()
205 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); in dpu_hw_intf_setup_timing_engine()
233 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, in dpu_hw_intf_setup_prg_fetch()
239 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); in dpu_hw_intf_setup_prg_fetch()
[all …]
A Ddpu_hw_sspp.c305 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, in dpu_hw_sspp_setup_format()
314 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
319 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
324 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
350 DPU_REG_WRITE(c, op_mode_off + idx, opmode); in dpu_hw_sspp_setup_format()
506 DPU_REG_WRITE(c, src_xy_off + idx, src_xy); in dpu_hw_sspp_setup_rects()
508 DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); in dpu_hw_sspp_setup_rects()
529 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
531 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
534 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, in dpu_hw_sspp_setup_sourceaddress()
[all …]
A Ddpu_hw_dspp.c38 DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); in dpu_setup_dspp_pcc()
42 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r); in dpu_setup_dspp_pcc()
43 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g); in dpu_setup_dspp_pcc()
44 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b); in dpu_setup_dspp_pcc()
46 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r); in dpu_setup_dspp_pcc()
47 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g); in dpu_setup_dspp_pcc()
48 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b); in dpu_setup_dspp_pcc()
50 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r); in dpu_setup_dspp_pcc()
51 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g); in dpu_setup_dspp_pcc()
52 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b); in dpu_setup_dspp_pcc()
[all …]
A Ddpu_hw_lm.c83 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); in dpu_hw_lm_setup_out()
90 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_out()
100 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, in dpu_hw_lm_setup_border_color()
103 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, in dpu_hw_lm_setup_border_color()
114 DPU_REG_WRITE(c, LM_MISR_CTRL, LM_MISR_CTRL_STATUS_CLEAR); in dpu_hw_lm_setup_misr()
123 DPU_REG_WRITE(c, LM_MISR_CTRL, config); in dpu_hw_lm_setup_misr()
125 DPU_REG_WRITE(c, LM_MISR_CTRL, 0); in dpu_hw_lm_setup_misr()
167 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config_sdm845()
183 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); in dpu_hw_lm_setup_blend_config()
185 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config()
[all …]
A Ddpu_hw_pingpong.c72 DPU_REG_WRITE(c, base + PP_DITHER_EN, 0); in dpu_hw_pp_setup_dither()
82 DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data); in dpu_hw_pp_setup_dither()
91 DPU_REG_WRITE(c, base + PP_DITHER_EN, 1); in dpu_hw_pp_setup_dither()
110 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); in dpu_hw_pp_setup_te_config()
113 DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq); in dpu_hw_pp_setup_te_config()
114 DPU_REG_WRITE(c, PP_START_POS, te->start_pos); in dpu_hw_pp_setup_te_config()
115 DPU_REG_WRITE(c, PP_SYNC_THRESH, in dpu_hw_pp_setup_te_config()
118 DPU_REG_WRITE(c, PP_SYNC_WRCOUNT, in dpu_hw_pp_setup_te_config()
127 DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG, in dpu_hw_pp_setup_autorefresh_config()
172 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable); in dpu_hw_pp_enable_te()
[all …]
A Ddpu_hw_ctl.c91 DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); in dpu_hw_ctl_trigger_start()
98 DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1); in dpu_hw_ctl_trigger_pending()
125 DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
128 DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
316 DPU_REG_WRITE(c, CTL_SW_RESET, 0x1); in dpu_hw_ctl_reset_control()
350 DPU_REG_WRITE(c, CTL_LAYER(mixer_id), 0); in dpu_hw_ctl_clear_all_blendstages()
356 DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0); in dpu_hw_ctl_clear_all_blendstages()
487 DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg); in dpu_hw_ctl_setup_blendstage()
507 DPU_REG_WRITE(c, CTL_TOP, mode_sel); in dpu_hw_ctl_intf_cfg_v1()
510 DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, in dpu_hw_ctl_intf_cfg_v1()
[all …]
A Ddpu_hw_top.c85 DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0); in dpu_hw_setup_split_pipe()
86 DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); in dpu_hw_setup_split_pipe()
87 DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); in dpu_hw_setup_split_pipe()
88 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); in dpu_hw_setup_split_pipe()
117 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
175 DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); in dpu_hw_setup_vsync_source()
208 DPU_REG_WRITE(c, wd_load_value, in dpu_hw_setup_vsync_source()
211 DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ in dpu_hw_setup_vsync_source()
215 DPU_REG_WRITE(c, wd_ctl2, reg); in dpu_hw_setup_vsync_source()
260 DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1); in dpu_hw_intf_audio_select()
A Ddpu_hw_vbif.c52 DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src); in dpu_hw_clear_errors()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
141 DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); in dpu_hw_set_halt_ctrl()
181 DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); in dpu_hw_set_qos_remap()
182 DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl); in dpu_hw_set_qos_remap()
197 DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val); in dpu_hw_set_write_gather_en()
A Ddpu_hw_interrupts.c173 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_core_irq()
240 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_enable_irq_locked()
242 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_enable_irq_locked()
289 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_disable_irq_locked()
291 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_disable_irq_locked()
315 DPU_REG_WRITE(&intr->hw, in dpu_clear_irqs()
333 DPU_REG_WRITE(&intr->hw, in dpu_disable_all_irqs()
369 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_core_irq_read()
A Ddpu_hw_merge3d.c47 DPU_REG_WRITE(c, MERGE_3D_MODE, 0); in dpu_hw_merge_3d_setup_3d_mode()
48 DPU_REG_WRITE(c, MERGE_3D_MUX, 0); in dpu_hw_merge_3d_setup_3d_mode()
51 DPU_REG_WRITE(c, MERGE_3D_MODE, data); in dpu_hw_merge_3d_setup_3d_mode()
A Ddpu_hw_util.h310 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) macro

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