| /linux/Documentation/devicetree/bindings/devfreq/ |
| A D | rk3399_dmc.txt | 43 clocks freq is half of DRAM clock), default
60 The controller, pi, PHY and DRAM clock will
77 the ODT on the DRAM side and controller side are
81 the DRAM side driver strength in ohms. Default
85 the DRAM side ODT strength in ohms. Default value
103 the ODT on the DRAM side and controller side are
107 the DRAM side driver strength in ohms. Default
111 the DRAM side ODT strength in ohms. Default value
129 ddr3_odt_dis_freq, the ODT on the DRAM side and
133 the DRAM side driver strength in ohms. Default
[all …]
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| /linux/Documentation/hid/ |
| A D | amd-sfh-hid.rst | 60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On
72 2. Data transfer via DRAM.
77 the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client
78 layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver
79 shall allocate minimum of 32 bytes DRAM space.
103 | | | Allocate the DRAM | Enable |
136 | | | Read the DRAM data for| | |
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| /linux/drivers/memory/tegra/ |
| A D | Kconfig | 22 Tegra20 chips. The EMC controls the external DRAM on the board.
33 Tegra30 chips. The EMC controls the external DRAM on the board.
45 Tegra124 chips. The EMC controls the external DRAM on the board.
59 Tegra210 chips. The EMC controls the external DRAM on the board.
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | allwinner,sun4i-a10-pll5-clk.yaml | 7 title: Allwinner A10 DRAM PLL Device Tree Bindings
19 The first output is the DRAM clock output, the second is meant
|
| /linux/sound/isa/gus/ |
| A D | gus_dram.c | 28 outsb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_poke()
64 insb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_peek()
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| /linux/drivers/memory/samsung/ |
| A D | Kconfig | 19 Frequency Scaling in DMC and DRAM. It also supports changing timings
20 of DRAM running with different frequency. The timings are calculated
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| /linux/Documentation/devicetree/bindings/firmware/ |
| A D | nvidia,tegra210-bpmp.txt | 6 (suspend to ram), and also offloading DRAM memory clock scaling on
23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
|
| /linux/arch/arm/ |
| A D | Kconfig-nommu | 14 hex '(S)DRAM Base Address' if SET_MEM_PARAM
18 hex '(S)DRAM SIZE' if SET_MEM_PARAM
|
| /linux/Documentation/devicetree/bindings/media/ |
| A D | allwinner,sun4i-a10-csi.yaml | 39 - description: The CSI DRAM clock
44 - description: The CSI DRAM clock
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| A D | nvidia,tegra186-mc.yaml | 20 encryption of traffic to and from DRAM via general security apertures are
21 available for video and other secure applications, as well as DRAM ECC for
|
| A D | samsung,exynos5422-dmc.yaml | 17 DRAM memory chips are connected. The driver is to monitor the controller in
53 phandle of the connected DRAM memory device. For more information please
|
| A D | calxeda-ddr-ctrlr.yaml | 12 purposes and to learn about the DRAM topology.
|
| /linux/Documentation/x86/ |
| A D | amd-memory-encryption.rst | 12 automatically decrypted when read from DRAM and encrypted when written to
13 DRAM. SME can therefore be used to protect the contents of DRAM from physical
|
| /linux/arch/arm64/boot/dts/broadcom/stingray/ |
| A D | stingray-board-base.dtsi | 22 &memory { /* Default DRAM banks */
|
| /linux/arch/arm/mach-lpc32xx/ |
| A D | suspend.S | 53 @ This guarantees a small windows where DRAM isn't busy
|
| /linux/drivers/edac/ |
| A D | Kconfig | 81 Support for error detection and correction of DRAM ECC errors on
90 Correctable errors into DRAM.
100 which trigger the DRAM ECC Read and Write respectively.
171 E3-1200 based DRAM controllers.
375 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
540 SoCs with ARM DMC-520 DRAM controller.
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| /linux/Documentation/arm/sa1100/ |
| A D | lart.rst | 6 applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
|
| /linux/Documentation/admin-guide/perf/ |
| A D | imx-ddr.rst | 5 There are no performance counters inside the DRAM controller, so performance
30 from different DRAM controller implementations, which is distinguished by quirks
|
| /linux/Documentation/devicetree/bindings/edac/ |
| A D | dmc-520.yaml | 13 DMC-520 node is defined to describe DRAM error detection and correction.
|
| /linux/Documentation/driver-api/ |
| A D | edac.rst | 18 The individual DRAM chips on a memory stick. These devices commonly
69 This is the name of the DRAM signal used to select the DRAM ranks to be
|
| /linux/Documentation/devicetree/bindings/nds32/ |
| A D | atl2c.txt | 7 reducing DRAM accesses.
|
| /linux/Documentation/vm/damon/ |
| A D | index.rst | 10 - *accurate* (the monitoring output is useful enough for DRAM level memory
|
| /linux/arch/x86/ras/ |
| A D | Kconfig | 13 have ECC DIMMs and doesn't have DRAM ECC checking enabled in the BIOS.
|
| /linux/Documentation/devicetree/bindings/arm/ |
| A D | fw-cfg.txt | 12 DTB that QEMU places at the bottom of the guest's DRAM.
|
| /linux/Documentation/devicetree/bindings/mmc/ |
| A D | amlogic,meson-gx.txt | 27 DRAM memory, like on the G12A dedicated SDIO controller.
|