1 #ifndef EDP_XML
2 #define EDP_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
31 Copyright (C) 2013-2021 by the following authors:
32 - Rob Clark <robdclark@gmail.com> (robclark)
33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
35 Permission is hereby granted, free of charge, to any person obtaining
36 a copy of this software and associated documentation files (the
37 "Software"), to deal in the Software without restriction, including
38 without limitation the rights to use, copy, modify, merge, publish,
39 distribute, sublicense, and/or sell copies of the Software, and to
40 permit persons to whom the Software is furnished to do so, subject to
41 the following conditions:
42
43 The above copyright notice and this permission notice (including the
44 next paragraph) shall be included in all copies or substantial
45 portions of the Software.
46
47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54 */
55
56
57 enum edp_color_depth {
58 EDP_6BIT = 0,
59 EDP_8BIT = 1,
60 EDP_10BIT = 2,
61 EDP_12BIT = 3,
62 EDP_16BIT = 4,
63 };
64
65 enum edp_component_format {
66 EDP_RGB = 0,
67 EDP_YUV422 = 1,
68 EDP_YUV444 = 2,
69 };
70
71 #define REG_EDP_MAINLINK_CTRL 0x00000004
72 #define EDP_MAINLINK_CTRL_ENABLE 0x00000001
73 #define EDP_MAINLINK_CTRL_RESET 0x00000002
74
75 #define REG_EDP_STATE_CTRL 0x00000008
76 #define EDP_STATE_CTRL_TRAIN_PATTERN_1 0x00000001
77 #define EDP_STATE_CTRL_TRAIN_PATTERN_2 0x00000002
78 #define EDP_STATE_CTRL_TRAIN_PATTERN_3 0x00000004
79 #define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS 0x00000008
80 #define EDP_STATE_CTRL_PRBS7 0x00000010
81 #define EDP_STATE_CTRL_CUSTOM_80_BIT_PATTERN 0x00000020
82 #define EDP_STATE_CTRL_SEND_VIDEO 0x00000040
83 #define EDP_STATE_CTRL_PUSH_IDLE 0x00000080
84
85 #define REG_EDP_CONFIGURATION_CTRL 0x0000000c
86 #define EDP_CONFIGURATION_CTRL_SYNC_CLK 0x00000001
87 #define EDP_CONFIGURATION_CTRL_STATIC_MVID 0x00000002
88 #define EDP_CONFIGURATION_CTRL_PROGRESSIVE 0x00000004
89 #define EDP_CONFIGURATION_CTRL_LANES__MASK 0x00000030
90 #define EDP_CONFIGURATION_CTRL_LANES__SHIFT 4
EDP_CONFIGURATION_CTRL_LANES(uint32_t val)91 static inline uint32_t EDP_CONFIGURATION_CTRL_LANES(uint32_t val)
92 {
93 return ((val) << EDP_CONFIGURATION_CTRL_LANES__SHIFT) & EDP_CONFIGURATION_CTRL_LANES__MASK;
94 }
95 #define EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING 0x00000040
96 #define EDP_CONFIGURATION_CTRL_COLOR__MASK 0x00000100
97 #define EDP_CONFIGURATION_CTRL_COLOR__SHIFT 8
EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val)98 static inline uint32_t EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val)
99 {
100 return ((val) << EDP_CONFIGURATION_CTRL_COLOR__SHIFT) & EDP_CONFIGURATION_CTRL_COLOR__MASK;
101 }
102
103 #define REG_EDP_SOFTWARE_MVID 0x00000014
104
105 #define REG_EDP_SOFTWARE_NVID 0x00000018
106
107 #define REG_EDP_TOTAL_HOR_VER 0x0000001c
108 #define EDP_TOTAL_HOR_VER_HORIZ__MASK 0x0000ffff
109 #define EDP_TOTAL_HOR_VER_HORIZ__SHIFT 0
EDP_TOTAL_HOR_VER_HORIZ(uint32_t val)110 static inline uint32_t EDP_TOTAL_HOR_VER_HORIZ(uint32_t val)
111 {
112 return ((val) << EDP_TOTAL_HOR_VER_HORIZ__SHIFT) & EDP_TOTAL_HOR_VER_HORIZ__MASK;
113 }
114 #define EDP_TOTAL_HOR_VER_VERT__MASK 0xffff0000
115 #define EDP_TOTAL_HOR_VER_VERT__SHIFT 16
EDP_TOTAL_HOR_VER_VERT(uint32_t val)116 static inline uint32_t EDP_TOTAL_HOR_VER_VERT(uint32_t val)
117 {
118 return ((val) << EDP_TOTAL_HOR_VER_VERT__SHIFT) & EDP_TOTAL_HOR_VER_VERT__MASK;
119 }
120
121 #define REG_EDP_START_HOR_VER_FROM_SYNC 0x00000020
122 #define EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK 0x0000ffff
123 #define EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT 0
EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val)124 static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val)
125 {
126 return ((val) << EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK;
127 }
128 #define EDP_START_HOR_VER_FROM_SYNC_VERT__MASK 0xffff0000
129 #define EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT 16
EDP_START_HOR_VER_FROM_SYNC_VERT(uint32_t val)130 static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_VERT(uint32_t val)
131 {
132 return ((val) << EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_VERT__MASK;
133 }
134
135 #define REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY 0x00000024
136 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK 0x00007fff
137 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT 0
EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ(uint32_t val)138 static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ(uint32_t val)
139 {
140 return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK;
141 }
142 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NHSYNC 0x00008000
143 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK 0x7fff0000
144 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT 16
EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT(uint32_t val)145 static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT(uint32_t val)
146 {
147 return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK;
148 }
149 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NVSYNC 0x80000000
150
151 #define REG_EDP_ACTIVE_HOR_VER 0x00000028
152 #define EDP_ACTIVE_HOR_VER_HORIZ__MASK 0x0000ffff
153 #define EDP_ACTIVE_HOR_VER_HORIZ__SHIFT 0
EDP_ACTIVE_HOR_VER_HORIZ(uint32_t val)154 static inline uint32_t EDP_ACTIVE_HOR_VER_HORIZ(uint32_t val)
155 {
156 return ((val) << EDP_ACTIVE_HOR_VER_HORIZ__SHIFT) & EDP_ACTIVE_HOR_VER_HORIZ__MASK;
157 }
158 #define EDP_ACTIVE_HOR_VER_VERT__MASK 0xffff0000
159 #define EDP_ACTIVE_HOR_VER_VERT__SHIFT 16
EDP_ACTIVE_HOR_VER_VERT(uint32_t val)160 static inline uint32_t EDP_ACTIVE_HOR_VER_VERT(uint32_t val)
161 {
162 return ((val) << EDP_ACTIVE_HOR_VER_VERT__SHIFT) & EDP_ACTIVE_HOR_VER_VERT__MASK;
163 }
164
165 #define REG_EDP_MISC1_MISC0 0x0000002c
166 #define EDP_MISC1_MISC0_MISC0__MASK 0x000000ff
167 #define EDP_MISC1_MISC0_MISC0__SHIFT 0
EDP_MISC1_MISC0_MISC0(uint32_t val)168 static inline uint32_t EDP_MISC1_MISC0_MISC0(uint32_t val)
169 {
170 return ((val) << EDP_MISC1_MISC0_MISC0__SHIFT) & EDP_MISC1_MISC0_MISC0__MASK;
171 }
172 #define EDP_MISC1_MISC0_SYNC 0x00000001
173 #define EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK 0x00000006
174 #define EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT 1
EDP_MISC1_MISC0_COMPONENT_FORMAT(enum edp_component_format val)175 static inline uint32_t EDP_MISC1_MISC0_COMPONENT_FORMAT(enum edp_component_format val)
176 {
177 return ((val) << EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT) & EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK;
178 }
179 #define EDP_MISC1_MISC0_CEA 0x00000008
180 #define EDP_MISC1_MISC0_BT709_5 0x00000010
181 #define EDP_MISC1_MISC0_COLOR__MASK 0x000000e0
182 #define EDP_MISC1_MISC0_COLOR__SHIFT 5
EDP_MISC1_MISC0_COLOR(enum edp_color_depth val)183 static inline uint32_t EDP_MISC1_MISC0_COLOR(enum edp_color_depth val)
184 {
185 return ((val) << EDP_MISC1_MISC0_COLOR__SHIFT) & EDP_MISC1_MISC0_COLOR__MASK;
186 }
187 #define EDP_MISC1_MISC0_MISC1__MASK 0x0000ff00
188 #define EDP_MISC1_MISC0_MISC1__SHIFT 8
EDP_MISC1_MISC0_MISC1(uint32_t val)189 static inline uint32_t EDP_MISC1_MISC0_MISC1(uint32_t val)
190 {
191 return ((val) << EDP_MISC1_MISC0_MISC1__SHIFT) & EDP_MISC1_MISC0_MISC1__MASK;
192 }
193 #define EDP_MISC1_MISC0_INTERLACED_ODD 0x00000100
194 #define EDP_MISC1_MISC0_STEREO__MASK 0x00000600
195 #define EDP_MISC1_MISC0_STEREO__SHIFT 9
EDP_MISC1_MISC0_STEREO(uint32_t val)196 static inline uint32_t EDP_MISC1_MISC0_STEREO(uint32_t val)
197 {
198 return ((val) << EDP_MISC1_MISC0_STEREO__SHIFT) & EDP_MISC1_MISC0_STEREO__MASK;
199 }
200
201 #define REG_EDP_PHY_CTRL 0x00000074
202 #define EDP_PHY_CTRL_SW_RESET_PLL 0x00000001
203 #define EDP_PHY_CTRL_SW_RESET 0x00000004
204
205 #define REG_EDP_MAINLINK_READY 0x00000084
206 #define EDP_MAINLINK_READY_TRAIN_PATTERN_1_READY 0x00000008
207 #define EDP_MAINLINK_READY_TRAIN_PATTERN_2_READY 0x00000010
208 #define EDP_MAINLINK_READY_TRAIN_PATTERN_3_READY 0x00000020
209
210 #define REG_EDP_AUX_CTRL 0x00000300
211 #define EDP_AUX_CTRL_ENABLE 0x00000001
212 #define EDP_AUX_CTRL_RESET 0x00000002
213
214 #define REG_EDP_INTERRUPT_REG_1 0x00000308
215 #define EDP_INTERRUPT_REG_1_HPD 0x00000001
216 #define EDP_INTERRUPT_REG_1_HPD_ACK 0x00000002
217 #define EDP_INTERRUPT_REG_1_HPD_EN 0x00000004
218 #define EDP_INTERRUPT_REG_1_AUX_I2C_DONE 0x00000008
219 #define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_ACK 0x00000010
220 #define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_EN 0x00000020
221 #define EDP_INTERRUPT_REG_1_WRONG_ADDR 0x00000040
222 #define EDP_INTERRUPT_REG_1_WRONG_ADDR_ACK 0x00000080
223 #define EDP_INTERRUPT_REG_1_WRONG_ADDR_EN 0x00000100
224 #define EDP_INTERRUPT_REG_1_TIMEOUT 0x00000200
225 #define EDP_INTERRUPT_REG_1_TIMEOUT_ACK 0x00000400
226 #define EDP_INTERRUPT_REG_1_TIMEOUT_EN 0x00000800
227 #define EDP_INTERRUPT_REG_1_NACK_DEFER 0x00001000
228 #define EDP_INTERRUPT_REG_1_NACK_DEFER_ACK 0x00002000
229 #define EDP_INTERRUPT_REG_1_NACK_DEFER_EN 0x00004000
230 #define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT 0x00008000
231 #define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_ACK 0x00010000
232 #define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_EN 0x00020000
233 #define EDP_INTERRUPT_REG_1_I2C_NACK 0x00040000
234 #define EDP_INTERRUPT_REG_1_I2C_NACK_ACK 0x00080000
235 #define EDP_INTERRUPT_REG_1_I2C_NACK_EN 0x00100000
236 #define EDP_INTERRUPT_REG_1_I2C_DEFER 0x00200000
237 #define EDP_INTERRUPT_REG_1_I2C_DEFER_ACK 0x00400000
238 #define EDP_INTERRUPT_REG_1_I2C_DEFER_EN 0x00800000
239 #define EDP_INTERRUPT_REG_1_PLL_UNLOCK 0x01000000
240 #define EDP_INTERRUPT_REG_1_PLL_UNLOCK_ACK 0x02000000
241 #define EDP_INTERRUPT_REG_1_PLL_UNLOCK_EN 0x04000000
242 #define EDP_INTERRUPT_REG_1_AUX_ERROR 0x08000000
243 #define EDP_INTERRUPT_REG_1_AUX_ERROR_ACK 0x10000000
244 #define EDP_INTERRUPT_REG_1_AUX_ERROR_EN 0x20000000
245
246 #define REG_EDP_INTERRUPT_REG_2 0x0000030c
247 #define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO 0x00000001
248 #define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_ACK 0x00000002
249 #define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_EN 0x00000004
250 #define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT 0x00000008
251 #define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_ACK 0x00000010
252 #define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_EN 0x00000020
253 #define EDP_INTERRUPT_REG_2_FRAME_END 0x00000200
254 #define EDP_INTERRUPT_REG_2_FRAME_END_ACK 0x00000080
255 #define EDP_INTERRUPT_REG_2_FRAME_END_EN 0x00000100
256 #define EDP_INTERRUPT_REG_2_CRC_UPDATED 0x00000200
257 #define EDP_INTERRUPT_REG_2_CRC_UPDATED_ACK 0x00000400
258 #define EDP_INTERRUPT_REG_2_CRC_UPDATED_EN 0x00000800
259
260 #define REG_EDP_INTERRUPT_TRANS_NUM 0x00000310
261
262 #define REG_EDP_AUX_DATA 0x00000314
263 #define EDP_AUX_DATA_READ 0x00000001
264 #define EDP_AUX_DATA_DATA__MASK 0x0000ff00
265 #define EDP_AUX_DATA_DATA__SHIFT 8
EDP_AUX_DATA_DATA(uint32_t val)266 static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val)
267 {
268 return ((val) << EDP_AUX_DATA_DATA__SHIFT) & EDP_AUX_DATA_DATA__MASK;
269 }
270 #define EDP_AUX_DATA_INDEX__MASK 0x00ff0000
271 #define EDP_AUX_DATA_INDEX__SHIFT 16
EDP_AUX_DATA_INDEX(uint32_t val)272 static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val)
273 {
274 return ((val) << EDP_AUX_DATA_INDEX__SHIFT) & EDP_AUX_DATA_INDEX__MASK;
275 }
276 #define EDP_AUX_DATA_INDEX_WRITE 0x80000000
277
278 #define REG_EDP_AUX_TRANS_CTRL 0x00000318
279 #define EDP_AUX_TRANS_CTRL_I2C 0x00000100
280 #define EDP_AUX_TRANS_CTRL_GO 0x00000200
281
282 #define REG_EDP_AUX_STATUS 0x00000324
283
REG_EDP_PHY_LN(uint32_t i0)284 static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; }
285
REG_EDP_PHY_LN_PD_CTL(uint32_t i0)286 static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; }
287
288 #define REG_EDP_PHY_GLB_VM_CFG0 0x00000510
289
290 #define REG_EDP_PHY_GLB_VM_CFG1 0x00000514
291
292 #define REG_EDP_PHY_GLB_MISC9 0x00000518
293
294 #define REG_EDP_PHY_GLB_CFG 0x00000528
295
296 #define REG_EDP_PHY_GLB_PD_CTL 0x0000052c
297
298 #define REG_EDP_PHY_GLB_PHY_STATUS 0x00000598
299
300 #define REG_EDP_28nm_PHY_PLL_REFCLK_CFG 0x00000000
301
302 #define REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
303
304 #define REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
305
306 #define REG_EDP_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
307
308 #define REG_EDP_28nm_PHY_PLL_VREG_CFG 0x00000010
309
310 #define REG_EDP_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
311
312 #define REG_EDP_28nm_PHY_PLL_DMUX_CFG 0x00000018
313
314 #define REG_EDP_28nm_PHY_PLL_AMUX_CFG 0x0000001c
315
316 #define REG_EDP_28nm_PHY_PLL_GLB_CFG 0x00000020
317 #define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
318 #define EDP_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
319 #define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
320 #define EDP_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
321
322 #define REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
323
324 #define REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
325
326 #define REG_EDP_28nm_PHY_PLL_LPFR_CFG 0x0000002c
327
328 #define REG_EDP_28nm_PHY_PLL_LPFC1_CFG 0x00000030
329
330 #define REG_EDP_28nm_PHY_PLL_LPFC2_CFG 0x00000034
331
332 #define REG_EDP_28nm_PHY_PLL_SDM_CFG0 0x00000038
333
334 #define REG_EDP_28nm_PHY_PLL_SDM_CFG1 0x0000003c
335
336 #define REG_EDP_28nm_PHY_PLL_SDM_CFG2 0x00000040
337
338 #define REG_EDP_28nm_PHY_PLL_SDM_CFG3 0x00000044
339
340 #define REG_EDP_28nm_PHY_PLL_SDM_CFG4 0x00000048
341
342 #define REG_EDP_28nm_PHY_PLL_SSC_CFG0 0x0000004c
343
344 #define REG_EDP_28nm_PHY_PLL_SSC_CFG1 0x00000050
345
346 #define REG_EDP_28nm_PHY_PLL_SSC_CFG2 0x00000054
347
348 #define REG_EDP_28nm_PHY_PLL_SSC_CFG3 0x00000058
349
350 #define REG_EDP_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
351
352 #define REG_EDP_28nm_PHY_PLL_LKDET_CFG1 0x00000060
353
354 #define REG_EDP_28nm_PHY_PLL_LKDET_CFG2 0x00000064
355
356 #define REG_EDP_28nm_PHY_PLL_TEST_CFG 0x00000068
357 #define EDP_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
358
359 #define REG_EDP_28nm_PHY_PLL_CAL_CFG0 0x0000006c
360
361 #define REG_EDP_28nm_PHY_PLL_CAL_CFG1 0x00000070
362
363 #define REG_EDP_28nm_PHY_PLL_CAL_CFG2 0x00000074
364
365 #define REG_EDP_28nm_PHY_PLL_CAL_CFG3 0x00000078
366
367 #define REG_EDP_28nm_PHY_PLL_CAL_CFG4 0x0000007c
368
369 #define REG_EDP_28nm_PHY_PLL_CAL_CFG5 0x00000080
370
371 #define REG_EDP_28nm_PHY_PLL_CAL_CFG6 0x00000084
372
373 #define REG_EDP_28nm_PHY_PLL_CAL_CFG7 0x00000088
374
375 #define REG_EDP_28nm_PHY_PLL_CAL_CFG8 0x0000008c
376
377 #define REG_EDP_28nm_PHY_PLL_CAL_CFG9 0x00000090
378
379 #define REG_EDP_28nm_PHY_PLL_CAL_CFG10 0x00000094
380
381 #define REG_EDP_28nm_PHY_PLL_CAL_CFG11 0x00000098
382
383 #define REG_EDP_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
384
385 #define REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
386
387
388 #endif /* EDP_XML */
389