Searched refs:EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG (Results 1 – 2 of 2) sorted by relevance
72 { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
415 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 macro
Completed in 7 milliseconds