1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // ak4642.c  --  AK4642/AK4643 ALSA Soc Audio driver
4 //
5 // Copyright (C) 2009 Renesas Solutions Corp.
6 // Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 //
8 // Based on wm8731.c by Richard Purdie
9 // Based on ak4535.c by Richard Purdie
10 // Based on wm8753.c by Liam Girdwood
11 
12 /* ** CAUTION **
13  *
14  * This is very simple driver.
15  * It can use headphone output / stereo input only
16  *
17  * AK4642 is tested.
18  * AK4643 is tested.
19  * AK4648 is tested.
20  */
21 
22 #include <linux/clk.h>
23 #include <linux/clk-provider.h>
24 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/module.h>
29 #include <linux/regmap.h>
30 #include <sound/soc.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 
34 #define PW_MGMT1	0x00
35 #define PW_MGMT2	0x01
36 #define SG_SL1		0x02
37 #define SG_SL2		0x03
38 #define MD_CTL1		0x04
39 #define MD_CTL2		0x05
40 #define TIMER		0x06
41 #define ALC_CTL1	0x07
42 #define ALC_CTL2	0x08
43 #define L_IVC		0x09
44 #define L_DVC		0x0a
45 #define ALC_CTL3	0x0b
46 #define R_IVC		0x0c
47 #define R_DVC		0x0d
48 #define MD_CTL3		0x0e
49 #define MD_CTL4		0x0f
50 #define PW_MGMT3	0x10
51 #define DF_S		0x11
52 #define FIL3_0		0x12
53 #define FIL3_1		0x13
54 #define FIL3_2		0x14
55 #define FIL3_3		0x15
56 #define EQ_0		0x16
57 #define EQ_1		0x17
58 #define EQ_2		0x18
59 #define EQ_3		0x19
60 #define EQ_4		0x1a
61 #define EQ_5		0x1b
62 #define FIL1_0		0x1c
63 #define FIL1_1		0x1d
64 #define FIL1_2		0x1e
65 #define FIL1_3		0x1f	/* The maximum valid register for ak4642 */
66 #define PW_MGMT4	0x20
67 #define MD_CTL5		0x21
68 #define LO_MS		0x22
69 #define HP_MS		0x23
70 #define SPK_MS		0x24	/* The maximum valid register for ak4643 */
71 #define EQ_FBEQAB	0x25
72 #define EQ_FBEQCD	0x26
73 #define EQ_FBEQE	0x27	/* The maximum valid register for ak4648 */
74 
75 /* PW_MGMT1*/
76 #define PMVCM		(1 << 6) /* VCOM Power Management */
77 #define PMMIN		(1 << 5) /* MIN Input Power Management */
78 #define PMDAC		(1 << 2) /* DAC Power Management */
79 #define PMADL		(1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
80 
81 /* PW_MGMT2 */
82 #define HPMTN		(1 << 6)
83 #define PMHPL		(1 << 5)
84 #define PMHPR		(1 << 4)
85 #define MS		(1 << 3) /* master/slave select */
86 #define MCKO		(1 << 1)
87 #define PMPLL		(1 << 0)
88 
89 #define PMHP_MASK	(PMHPL | PMHPR)
90 #define PMHP		PMHP_MASK
91 
92 /* PW_MGMT3 */
93 #define PMADR		(1 << 0) /* MIC L / ADC R Power Management */
94 
95 /* SG_SL1 */
96 #define MINS		(1 << 6) /* Switch from MIN to Speaker */
97 #define DACL		(1 << 4) /* Switch from DAC to Stereo or Receiver */
98 #define PMMP		(1 << 2) /* MPWR pin Power Management */
99 #define MGAIN0		(1 << 0) /* MIC amp gain*/
100 
101 /* SG_SL2 */
102 #define LOPS		(1 << 6) /* Stero Line-out Power Save Mode */
103 
104 /* TIMER */
105 #define ZTM(param)	((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
106 #define WTM(param)	(((param & 0x4) << 4) | ((param & 0x3) << 2))
107 
108 /* ALC_CTL1 */
109 #define ALC		(1 << 5) /* ALC Enable */
110 #define LMTH0		(1 << 0) /* ALC Limiter / Recovery Level */
111 
112 /* MD_CTL1 */
113 #define PLL3		(1 << 7)
114 #define PLL2		(1 << 6)
115 #define PLL1		(1 << 5)
116 #define PLL0		(1 << 4)
117 #define PLL_MASK	(PLL3 | PLL2 | PLL1 | PLL0)
118 
119 #define BCKO_MASK	(1 << 3)
120 #define BCKO_64		BCKO_MASK
121 
122 #define DIF_MASK	(3 << 0)
123 #define DSP		(0 << 0)
124 #define RIGHT_J		(1 << 0)
125 #define LEFT_J		(2 << 0)
126 #define I2S		(3 << 0)
127 
128 /* MD_CTL2 */
129 #define FSs(val)	(((val & 0x7) << 0) | ((val & 0x8) << 2))
130 #define PSs(val)	((val & 0x3) << 6)
131 
132 /* MD_CTL3 */
133 #define BST1		(1 << 3)
134 
135 /* MD_CTL4 */
136 #define DACH		(1 << 0)
137 
138 struct ak4642_drvdata {
139 	const struct regmap_config *regmap_config;
140 	int extended_frequencies;
141 };
142 
143 struct ak4642_priv {
144 	const struct ak4642_drvdata *drvdata;
145 	struct clk *mcko;
146 };
147 
148 /*
149  * Playback Volume (table 39)
150  *
151  * max : 0x00 : +12.0 dB
152  *       ( 0.5 dB step )
153  * min : 0xFE : -115.0 dB
154  * mute: 0xFF
155  */
156 static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
157 
158 static const struct snd_kcontrol_new ak4642_snd_controls[] = {
159 
160 	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
161 			 0, 0xFF, 1, out_tlv),
162 	SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
163 	SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
164 };
165 
166 static const struct snd_kcontrol_new ak4642_headphone_control =
167 	SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
168 
169 static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
170 	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
171 };
172 
173 /* event handlers */
ak4642_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)174 static int ak4642_lout_event(struct snd_soc_dapm_widget *w,
175 			     struct snd_kcontrol *kcontrol, int event)
176 {
177 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
178 
179 	switch (event) {
180 	case SND_SOC_DAPM_PRE_PMD:
181 	case SND_SOC_DAPM_PRE_PMU:
182 		/* Power save mode ON */
183 		snd_soc_component_update_bits(component, SG_SL2, LOPS, LOPS);
184 		break;
185 	case SND_SOC_DAPM_POST_PMU:
186 	case SND_SOC_DAPM_POST_PMD:
187 		/* Power save mode OFF */
188 		msleep(300);
189 		snd_soc_component_update_bits(component, SG_SL2, LOPS, 0);
190 		break;
191 	}
192 
193 	return 0;
194 }
195 
196 static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
197 
198 	/* Outputs */
199 	SND_SOC_DAPM_OUTPUT("HPOUTL"),
200 	SND_SOC_DAPM_OUTPUT("HPOUTR"),
201 	SND_SOC_DAPM_OUTPUT("LINEOUT"),
202 
203 	SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
204 	SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
205 	SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
206 			    &ak4642_headphone_control),
207 
208 	SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
209 
210 	SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0,
211 			   &ak4642_lout_mixer_controls[0],
212 			   ARRAY_SIZE(ak4642_lout_mixer_controls),
213 			   ak4642_lout_event,
214 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
215 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
216 
217 	/* DAC */
218 	SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0),
219 };
220 
221 static const struct snd_soc_dapm_route ak4642_intercon[] = {
222 
223 	/* Outputs */
224 	{"HPOUTL", NULL, "HPL Out"},
225 	{"HPOUTR", NULL, "HPR Out"},
226 	{"LINEOUT", NULL, "LINEOUT Mixer"},
227 
228 	{"HPL Out", NULL, "Headphone Enable"},
229 	{"HPR Out", NULL, "Headphone Enable"},
230 
231 	{"Headphone Enable", "Switch", "DACH"},
232 
233 	{"DACH", NULL, "DAC"},
234 
235 	{"LINEOUT Mixer", "DACL", "DAC"},
236 
237 	{ "DAC", NULL, "Playback" },
238 };
239 
240 /*
241  * ak4642 register cache
242  */
243 static const struct reg_default ak4643_reg[] = {
244 	{  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
245 	{  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
246 	{  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
247 	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
248 	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
249 	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
250 	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
251 	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
252 	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
253 	{ 36, 0x00 },
254 };
255 
256 /* The default settings for 0x0 ~ 0x1f registers are the same for ak4642
257    and ak4643. So we reuse the ak4643 reg_default for ak4642.
258    The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643,
259    so define NUM_AK4642_REG_DEFAULTS for ak4642.
260 */
261 #define ak4642_reg ak4643_reg
262 #define NUM_AK4642_REG_DEFAULTS	(FIL1_3 + 1)
263 
264 static const struct reg_default ak4648_reg[] = {
265 	{  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
266 	{  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
267 	{  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
268 	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
269 	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
270 	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
271 	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
272 	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
273 	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
274 	{ 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
275 };
276 
ak4642_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)277 static int ak4642_dai_startup(struct snd_pcm_substream *substream,
278 			      struct snd_soc_dai *dai)
279 {
280 	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
281 	struct snd_soc_component *component = dai->component;
282 
283 	if (is_play) {
284 		/*
285 		 * start headphone output
286 		 *
287 		 * PLL, Master Mode
288 		 * Audio I/F Format :MSB justified (ADC & DAC)
289 		 * Bass Boost Level : Middle
290 		 *
291 		 * This operation came from example code of
292 		 * "ASAHI KASEI AK4642" (japanese) manual p97.
293 		 */
294 		snd_soc_component_write(component, L_IVC, 0x91); /* volume */
295 		snd_soc_component_write(component, R_IVC, 0x91); /* volume */
296 	} else {
297 		/*
298 		 * start stereo input
299 		 *
300 		 * PLL Master Mode
301 		 * Audio I/F Format:MSB justified (ADC & DAC)
302 		 * Pre MIC AMP:+20dB
303 		 * MIC Power On
304 		 * ALC setting:Refer to Table 35
305 		 * ALC bit=“1”
306 		 *
307 		 * This operation came from example code of
308 		 * "ASAHI KASEI AK4642" (japanese) manual p94.
309 		 */
310 		snd_soc_component_update_bits(component, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
311 		snd_soc_component_write(component, TIMER, ZTM(0x3) | WTM(0x3));
312 		snd_soc_component_write(component, ALC_CTL1, ALC | LMTH0);
313 		snd_soc_component_update_bits(component, PW_MGMT1, PMADL, PMADL);
314 		snd_soc_component_update_bits(component, PW_MGMT3, PMADR, PMADR);
315 	}
316 
317 	return 0;
318 }
319 
ak4642_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)320 static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
321 			       struct snd_soc_dai *dai)
322 {
323 	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
324 	struct snd_soc_component *component = dai->component;
325 
326 	if (is_play) {
327 	} else {
328 		/* stop stereo input */
329 		snd_soc_component_update_bits(component, PW_MGMT1, PMADL, 0);
330 		snd_soc_component_update_bits(component, PW_MGMT3, PMADR, 0);
331 		snd_soc_component_update_bits(component, ALC_CTL1, ALC, 0);
332 	}
333 }
334 
ak4642_dai_set_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)335 static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
336 	int clk_id, unsigned int freq, int dir)
337 {
338 	struct snd_soc_component *component = codec_dai->component;
339 	struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
340 	u8 pll;
341 	int extended_freq = 0;
342 
343 	switch (freq) {
344 	case 11289600:
345 		pll = PLL2;
346 		break;
347 	case 12288000:
348 		pll = PLL2 | PLL0;
349 		break;
350 	case 12000000:
351 		pll = PLL2 | PLL1;
352 		break;
353 	case 24000000:
354 		pll = PLL2 | PLL1 | PLL0;
355 		break;
356 	case 13500000:
357 		pll = PLL3 | PLL2;
358 		break;
359 	case 27000000:
360 		pll = PLL3 | PLL2 | PLL0;
361 		break;
362 	case 19200000:
363 		pll = PLL3;
364 		extended_freq = 1;
365 		break;
366 	case 13000000:
367 		pll = PLL3 | PLL2 | PLL1;
368 		extended_freq = 1;
369 		break;
370 	case 26000000:
371 		pll = PLL3 | PLL2 | PLL1 | PLL0;
372 		extended_freq = 1;
373 		break;
374 	default:
375 		return -EINVAL;
376 	}
377 
378 	if (extended_freq && !priv->drvdata->extended_frequencies)
379 		return -EINVAL;
380 
381 	snd_soc_component_update_bits(component, MD_CTL1, PLL_MASK, pll);
382 
383 	return 0;
384 }
385 
ak4642_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)386 static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
387 {
388 	struct snd_soc_component *component = dai->component;
389 	u8 data;
390 	u8 bcko;
391 
392 	data = MCKO | PMPLL; /* use MCKO */
393 	bcko = 0;
394 
395 	/* set clocking for audio interface */
396 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
397 	case SND_SOC_DAIFMT_CBP_CFP:
398 		data |= MS;
399 		bcko = BCKO_64;
400 		break;
401 	case SND_SOC_DAIFMT_CBC_CFC:
402 		break;
403 	default:
404 		return -EINVAL;
405 	}
406 	snd_soc_component_update_bits(component, PW_MGMT2, MS | MCKO | PMPLL, data);
407 	snd_soc_component_update_bits(component, MD_CTL1, BCKO_MASK, bcko);
408 
409 	/* format type */
410 	data = 0;
411 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
412 	case SND_SOC_DAIFMT_LEFT_J:
413 		data = LEFT_J;
414 		break;
415 	case SND_SOC_DAIFMT_I2S:
416 		data = I2S;
417 		break;
418 	/* FIXME
419 	 * Please add RIGHT_J / DSP support here
420 	 */
421 	default:
422 		return -EINVAL;
423 	}
424 	snd_soc_component_update_bits(component, MD_CTL1, DIF_MASK, data);
425 
426 	return 0;
427 }
428 
ak4642_set_mcko(struct snd_soc_component * component,u32 frequency)429 static int ak4642_set_mcko(struct snd_soc_component *component,
430 			   u32 frequency)
431 {
432 	static const u32 fs_list[] = {
433 		[0] = 8000,
434 		[1] = 12000,
435 		[2] = 16000,
436 		[3] = 24000,
437 		[4] = 7350,
438 		[5] = 11025,
439 		[6] = 14700,
440 		[7] = 22050,
441 		[10] = 32000,
442 		[11] = 48000,
443 		[14] = 29400,
444 		[15] = 44100,
445 	};
446 	static const u32 ps_list[] = {
447 		[0] = 256,
448 		[1] = 128,
449 		[2] = 64,
450 		[3] = 32
451 	};
452 	int ps, fs;
453 
454 	for (ps = 0; ps < ARRAY_SIZE(ps_list); ps++) {
455 		for (fs = 0; fs < ARRAY_SIZE(fs_list); fs++) {
456 			if (frequency == ps_list[ps] * fs_list[fs]) {
457 				snd_soc_component_write(component, MD_CTL2,
458 					      PSs(ps) | FSs(fs));
459 				return 0;
460 			}
461 		}
462 	}
463 
464 	return 0;
465 }
466 
ak4642_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)467 static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
468 				struct snd_pcm_hw_params *params,
469 				struct snd_soc_dai *dai)
470 {
471 	struct snd_soc_component *component = dai->component;
472 	struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
473 	u32 rate = clk_get_rate(priv->mcko);
474 
475 	if (!rate)
476 		rate = params_rate(params) * 256;
477 
478 	return ak4642_set_mcko(component, rate);
479 }
480 
ak4642_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)481 static int ak4642_set_bias_level(struct snd_soc_component *component,
482 				 enum snd_soc_bias_level level)
483 {
484 	switch (level) {
485 	case SND_SOC_BIAS_OFF:
486 		snd_soc_component_write(component, PW_MGMT1, 0x00);
487 		break;
488 	default:
489 		snd_soc_component_update_bits(component, PW_MGMT1, PMVCM, PMVCM);
490 		break;
491 	}
492 
493 	return 0;
494 }
495 
496 static const struct snd_soc_dai_ops ak4642_dai_ops = {
497 	.startup	= ak4642_dai_startup,
498 	.shutdown	= ak4642_dai_shutdown,
499 	.set_sysclk	= ak4642_dai_set_sysclk,
500 	.set_fmt	= ak4642_dai_set_fmt,
501 	.hw_params	= ak4642_dai_hw_params,
502 };
503 
504 static struct snd_soc_dai_driver ak4642_dai = {
505 	.name = "ak4642-hifi",
506 	.playback = {
507 		.stream_name = "Playback",
508 		.channels_min = 2,
509 		.channels_max = 2,
510 		.rates = SNDRV_PCM_RATE_8000_48000,
511 		.formats = SNDRV_PCM_FMTBIT_S16_LE },
512 	.capture = {
513 		.stream_name = "Capture",
514 		.channels_min = 2,
515 		.channels_max = 2,
516 		.rates = SNDRV_PCM_RATE_8000_48000,
517 		.formats = SNDRV_PCM_FMTBIT_S16_LE },
518 	.ops = &ak4642_dai_ops,
519 	.symmetric_rate = 1,
520 };
521 
ak4642_suspend(struct snd_soc_component * component)522 static int ak4642_suspend(struct snd_soc_component *component)
523 {
524 	struct regmap *regmap = dev_get_regmap(component->dev, NULL);
525 
526 	regcache_cache_only(regmap, true);
527 	regcache_mark_dirty(regmap);
528 	return 0;
529 }
530 
ak4642_resume(struct snd_soc_component * component)531 static int ak4642_resume(struct snd_soc_component *component)
532 {
533 	struct regmap *regmap = dev_get_regmap(component->dev, NULL);
534 
535 	regcache_cache_only(regmap, false);
536 	regcache_sync(regmap);
537 	return 0;
538 }
ak4642_probe(struct snd_soc_component * component)539 static int ak4642_probe(struct snd_soc_component *component)
540 {
541 	struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
542 
543 	if (priv->mcko)
544 		ak4642_set_mcko(component, clk_get_rate(priv->mcko));
545 
546 	return 0;
547 }
548 
549 static const struct snd_soc_component_driver soc_component_dev_ak4642 = {
550 	.probe			= ak4642_probe,
551 	.suspend		= ak4642_suspend,
552 	.resume			= ak4642_resume,
553 	.set_bias_level		= ak4642_set_bias_level,
554 	.controls		= ak4642_snd_controls,
555 	.num_controls		= ARRAY_SIZE(ak4642_snd_controls),
556 	.dapm_widgets		= ak4642_dapm_widgets,
557 	.num_dapm_widgets	= ARRAY_SIZE(ak4642_dapm_widgets),
558 	.dapm_routes		= ak4642_intercon,
559 	.num_dapm_routes	= ARRAY_SIZE(ak4642_intercon),
560 	.idle_bias_on		= 1,
561 	.endianness		= 1,
562 	.non_legacy_dai_naming	= 1,
563 };
564 
565 static const struct regmap_config ak4642_regmap = {
566 	.reg_bits		= 8,
567 	.val_bits		= 8,
568 	.max_register		= FIL1_3,
569 	.reg_defaults		= ak4642_reg,
570 	.num_reg_defaults	= NUM_AK4642_REG_DEFAULTS,
571 	.cache_type		= REGCACHE_RBTREE,
572 };
573 
574 static const struct regmap_config ak4643_regmap = {
575 	.reg_bits		= 8,
576 	.val_bits		= 8,
577 	.max_register		= SPK_MS,
578 	.reg_defaults		= ak4643_reg,
579 	.num_reg_defaults	= ARRAY_SIZE(ak4643_reg),
580 	.cache_type		= REGCACHE_RBTREE,
581 };
582 
583 static const struct regmap_config ak4648_regmap = {
584 	.reg_bits		= 8,
585 	.val_bits		= 8,
586 	.max_register		= EQ_FBEQE,
587 	.reg_defaults		= ak4648_reg,
588 	.num_reg_defaults	= ARRAY_SIZE(ak4648_reg),
589 	.cache_type		= REGCACHE_RBTREE,
590 };
591 
592 static const struct ak4642_drvdata ak4642_drvdata = {
593 	.regmap_config = &ak4642_regmap,
594 };
595 
596 static const struct ak4642_drvdata ak4643_drvdata = {
597 	.regmap_config = &ak4643_regmap,
598 };
599 
600 static const struct ak4642_drvdata ak4648_drvdata = {
601 	.regmap_config = &ak4648_regmap,
602 	.extended_frequencies = 1,
603 };
604 
605 #ifdef CONFIG_COMMON_CLK
ak4642_of_parse_mcko(struct device * dev)606 static struct clk *ak4642_of_parse_mcko(struct device *dev)
607 {
608 	struct device_node *np = dev->of_node;
609 	struct clk *clk;
610 	const char *clk_name = np->name;
611 	const char *parent_clk_name = NULL;
612 	u32 rate;
613 
614 	if (of_property_read_u32(np, "clock-frequency", &rate))
615 		return NULL;
616 
617 	if (of_property_read_bool(np, "clocks"))
618 		parent_clk_name = of_clk_get_parent_name(np, 0);
619 
620 	of_property_read_string(np, "clock-output-names", &clk_name);
621 
622 	clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate);
623 	if (!IS_ERR(clk))
624 		of_clk_add_provider(np, of_clk_src_simple_get, clk);
625 
626 	return clk;
627 }
628 #else
629 #define ak4642_of_parse_mcko(d) 0
630 #endif
631 
632 static const struct of_device_id ak4642_of_match[];
ak4642_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)633 static int ak4642_i2c_probe(struct i2c_client *i2c,
634 			    const struct i2c_device_id *id)
635 {
636 	struct device *dev = &i2c->dev;
637 	struct device_node *np = dev->of_node;
638 	const struct ak4642_drvdata *drvdata = NULL;
639 	struct regmap *regmap;
640 	struct ak4642_priv *priv;
641 	struct clk *mcko = NULL;
642 
643 	if (np) {
644 		const struct of_device_id *of_id;
645 
646 		mcko = ak4642_of_parse_mcko(dev);
647 		if (IS_ERR(mcko))
648 			mcko = NULL;
649 
650 		of_id = of_match_device(ak4642_of_match, dev);
651 		if (of_id)
652 			drvdata = of_id->data;
653 	} else {
654 		drvdata = (const struct ak4642_drvdata *)id->driver_data;
655 	}
656 
657 	if (!drvdata) {
658 		dev_err(dev, "Unknown device type\n");
659 		return -EINVAL;
660 	}
661 
662 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
663 	if (!priv)
664 		return -ENOMEM;
665 
666 	priv->drvdata = drvdata;
667 	priv->mcko = mcko;
668 
669 	i2c_set_clientdata(i2c, priv);
670 
671 	regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
672 	if (IS_ERR(regmap))
673 		return PTR_ERR(regmap);
674 
675 	return devm_snd_soc_register_component(dev,
676 				&soc_component_dev_ak4642, &ak4642_dai, 1);
677 }
678 
679 static const struct of_device_id ak4642_of_match[] = {
680 	{ .compatible = "asahi-kasei,ak4642",	.data = &ak4642_drvdata},
681 	{ .compatible = "asahi-kasei,ak4643",	.data = &ak4643_drvdata},
682 	{ .compatible = "asahi-kasei,ak4648",	.data = &ak4648_drvdata},
683 	{},
684 };
685 MODULE_DEVICE_TABLE(of, ak4642_of_match);
686 
687 static const struct i2c_device_id ak4642_i2c_id[] = {
688 	{ "ak4642", (kernel_ulong_t)&ak4642_drvdata },
689 	{ "ak4643", (kernel_ulong_t)&ak4643_drvdata },
690 	{ "ak4648", (kernel_ulong_t)&ak4648_drvdata },
691 	{ }
692 };
693 MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
694 
695 static struct i2c_driver ak4642_i2c_driver = {
696 	.driver = {
697 		.name = "ak4642-codec",
698 		.of_match_table = ak4642_of_match,
699 	},
700 	.probe		= ak4642_i2c_probe,
701 	.id_table	= ak4642_i2c_id,
702 };
703 
704 module_i2c_driver(ak4642_i2c_driver);
705 
706 MODULE_DESCRIPTION("Soc AK4642 driver");
707 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
708 MODULE_LICENSE("GPL v2");
709