Searched refs:FORMAT_CONTROL (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_dpp.c | 60 REG_SET_2(FORMAT_CONTROL, 0, in dpp201_cnv_setup()
64 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp201_cnv_setup()
65 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp201_cnv_setup()
66 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp201_cnv_setup()
67 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp201_cnv_setup()
165 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dpp.c | 113 REG_SET_2(FORMAT_CONTROL, 0, in dpp2_cnv_setup()
122 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
123 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
224 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp2_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dpp.c | 193 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
197 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp3_cnv_setup()
198 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp3_cnv_setup()
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp3_cnv_setup()
200 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp3_cnv_setup()
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); in dpp3_cnv_setup()
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); in dpp3_cnv_setup()
204 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); in dpp3_cnv_setup()
308 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp3_cnv_setup()
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| A D | dcn30_dpp.h | 134 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dpp.c | 312 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
318 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
390 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
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| A D | dcn10_ipp.h | 35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
189 uint32_t FORMAT_CONTROL; member
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| A D | dcn10_dpp_cm.c | 714 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
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| A D | dcn10_dpp.h | 119 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
1338 uint32_t FORMAT_CONTROL; \
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