Searched refs:Fld (Results 1 – 5 of 5) sorted by relevance
| /linux/arch/arm/mach-sa1100/include/mach/ |
| A D | SA-1100.h | 137 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
177 #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
179 #define UDCWC_WC Fld (4, 0) /* Write Count */
181 #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
337 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
338 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
378 #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
1448 Fld (16, ((Nb) Modulo 2)*16)
1516 Fld (15, (Nb)*16)
1543 #define MDREFR_TRASR Fld (4, 0)
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| A D | bitfield.h | 46 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
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| /linux/arch/arm/mach-pxa/include/mach/ |
| A D | regs-lcd.h | 89 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
92 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
95 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
98 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
101 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
104 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */
107 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
110 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
126 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
129 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
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| A D | bitfield.h | 47 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
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| /linux/arch/arm/include/asm/hardware/ |
| A D | sa1111.h | 67 #define SMCR_DRAC Fld(3, 2)
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