Searched refs:GCC_PCIE_1_PHY_BCR (Results 1 – 20 of 20) sorted by relevance
| /linux/include/dt-bindings/reset/ |
| A D | qcom,gcc-apq8084.h | 93 #define GCC_PCIE_1_PHY_BCR 84 macro
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| /linux/include/dt-bindings/clock/ |
| A D | qcom,gcc-sc7280.h | 212 #define GCC_PCIE_1_PHY_BCR 3 macro
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| A D | qcom,gcc-sdm845.h | 229 #define GCC_PCIE_1_PHY_BCR 25 macro
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| A D | qcom,gcc-sm8150.h | 220 #define GCC_PCIE_1_PHY_BCR 7 macro
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| A D | qcom,gcc-sm8250.h | 224 #define GCC_PCIE_1_PHY_BCR 12 macro
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| A D | qcom,gcc-sm8350.h | 227 #define GCC_PCIE_1_PHY_BCR 12 macro
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| A D | qcom,gcc-sc8180x.h | 257 #define GCC_PCIE_1_PHY_BCR 7 macro
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| A D | qcom,gcc-msm8996.h | 322 #define GCC_PCIE_1_PHY_BCR 82 macro
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| /linux/drivers/clk/qcom/ |
| A D | gcc-apq8084.c | 3565 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
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| A D | gcc-msm8996.c | 3581 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
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| A D | gcc-sc7280.c | 3410 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
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| A D | gcc-sdm845.c | 3533 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
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| A D | gcc-sm8250.c | 3549 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
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| A D | gcc-sm8150.c | 3692 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
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| A D | gcc-sm8350.c | 3758 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
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| A D | gcc-sc8180x.c | 4497 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
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| /linux/arch/arm64/boot/dts/qcom/ |
| A D | msm8996.dtsi | 623 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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| A D | sc7280.dtsi | 1658 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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| A D | sm8250.dtsi | 1554 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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| A D | sdm845.dtsi | 2170 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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