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/linux/Documentation/devicetree/bindings/interrupt-controller/
A Dmti,gic.yaml14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
70 timers, and a watchdog. Currently only the GIC Timer is supported.
77 Interrupt for the GIC local timer, so normally it's suppose to be of
A Darm,gic.yaml13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
87 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
96 Specifies base physical address(s) and size of the GIC registers. The
98 is the GIC cpu interface register base and size.
102 registers. The first additional region is the GIC virtual interface
103 control register base and size. The 2nd additional region is the GIC
112 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
118 regions, used when the GIC doesn't have banked registers. The offset
127 description: List of names for the GIC clock input(s). Valid clock names
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A Dbrcm,bcm7120-l2-intc.txt4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
32 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
38 7 ---------------------|---|===========> GIC interrupt 66
44 |===========> GIC interrupt 64
A Dmarvell,gicp.txt4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
A Dqcom,pdc.txt7 well detect interrupts when the GIC is non-operational.
9 GIC is parent interrupt controller at the highest level. Platform interrupt
13 with the GIC interrupt. See example below.
54 The second element is the GIC hwirq number for the PDC port.
68 DT binding of a device that wants to use the GIC SPI 514 as a wakeup
A Dti,omap4-wugen-mpu4 routes interrupts to the GIC, and also serves as a wakeup source. It
18 - Because this HW ultimately routes interrupts to the GIC, the
19 interrupt specifier must be that of the GIC.
A Dmediatek,cirq.txt4 work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
6 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
18 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
A Dnvidia,tegra20-ictlr.txt4 interrupts to the GIC, and also serves as a wakeup source. It is also
25 - Because this HW ultimately routes interrupts to the GIC, the
26 interrupt specifier must be that of the GIC.
A Dsocionext,uniphier-aidet.yaml10 UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC
11 (Generic Interrupt Controller). GIC itself can handle only high level and
42 interrupt number of GIC). The second cell specifies the trigger type as
A Drenesas,rza1-irqc.yaml14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
A Dmarvell,icu.txt6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
39 - msi-parent: Should point to the GICP controller, the GIC extension
A Darm,gic-v3.yaml73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
A Dmarvell,armada-8k-pic.txt6 typically connected to the GIC as the primary interrupt controller.
15 typically the GIC
A Dmarvell,odmi-controller.txt23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
27 for details about the GIC Device Tree binding.
A Dmstar,mst-intc.yaml14 interrupt controllers that routes interrupts to the GIC.
28 Use the same format as specified by GIC in arm,gic.yaml.
A Dmarvell,armada-370-xp-mpic.txt24 connected as a slave to the Cortex-A9 GIC. The provided interrupt
25 indicate to which GIC interrupt the MPIC output is connected.
A Dmediatek,sysirq.txt3 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
29 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
/linux/arch/mips/boot/dts/mti/
A Dsead3.dts64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
/linux/drivers/net/ethernet/renesas/
A Dravb_ptp.c202 ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0); in ravb_ptp_extts()
258 ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); in ravb_ptp_perout()
270 ravb_modify(ndev, GIC, GIC_PTME, 0); in ravb_ptp_perout()
311 gis &= ravb_read(ndev, GIC); in ravb_ptp_interrupt()
354 ravb_write(ndev, 0, GIC); in ravb_ptp_stop()
/linux/Documentation/virt/kvm/devices/
A Darm-vgic.rst27 Base address in the guest physical address space of the GIC distributor
32 Base address in the guest physical address space of the GIC virtual cpu
110 a GIC without the security extensions expose group 0 and group 1 active
132 this GIC instance, ranging from 64 to 1024, in increments of 32.
138 -EBUSY Value has already be set, or GIC has already been initialized
A Dvcpu.rst51 -ENODEV PMUv3 not supported or GIC not initialized
58 virtual GIC implementation, this must be done after initializing the in-kernel
70 -ENODEV PMUv3 not supported or GIC not initialized
127 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
/linux/Documentation/devicetree/bindings/arm/freescale/
A Dfsl,vf610-mscm-ir.txt19 Flags get passed only when using GIC as parent. Flags
20 encoding as documented by the GIC bindings.
/linux/arch/arm/boot/dts/
A Darm-realview-eb.dts34 * This is the core tile with the CPU and GIC etc for the
64 * to the GIC on the core tile.
/linux/Documentation/devicetree/bindings/misc/
A Dfsl,qoriq-mc.txt38 For GICv3 and GIC ITS bindings, see:
127 - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
134 associated with the listed GIC ITS, with the msi-specifier
/linux/Documentation/devicetree/bindings/timer/
A Darm,arch_timer.yaml17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC

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