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Searched refs:GIC_CPU_CTRL (Results 1 – 6 of 6) sorted by relevance

/linux/arch/arm/mach-oxnas/
A Dplatsmp.c27 #define GIC_CPU_CTRL 0x00 macro
48 gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL); in ox820_boot_secondary()
/linux/arch/arm/mach-tegra/
A Dirq.c51 writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); in tegra_gic_notifier()
/linux/arch/arm64/kvm/vgic/
A Dvgic-mmio-v2.c273 case GIC_CPU_CTRL: in vgic_mmio_read_vcpuif()
320 case GIC_CPU_CTRL: in vgic_mmio_write_vcpuif()
456 REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
/linux/include/linux/irqchip/
A Darm-gic.h10 #define GIC_CPU_CTRL 0x00 macro
/linux/drivers/irqchip/
A Dirq-gic.c462 bypass = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
465 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
541 val = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_down()
543 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_down()
A Dirq-hip04.c293 writel_relaxed(1, base + GIC_CPU_CTRL); in hip04_irq_cpu_init()

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