Searched refs:HCLK (Results 1 – 20 of 20) sorted by relevance
| /linux/Documentation/devicetree/bindings/mtd/ |
| A D | fsmc-nand.txt | 19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | st,nomadik.txt | 34 HCLK nodes: these represent the clock gates on individual
35 lines from the HCLK clock tree and the gate for individual
38 Requires properties for the HCLK nodes:
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| /linux/drivers/clk/samsung/ |
| A D | clk-s3c2410.c | 108 ALIAS(HCLK, NULL, "hclk"),
162 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
231 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
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| A D | clk-s3c2412.c | 64 DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
154 ALIAS(HCLK, NULL, "hclk"),
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| A D | clk-s3c2443.c | 101 DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
150 ALIAS(HCLK, NULL, "hclk"),
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| A D | clk-s3c64xx.c | 163 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
317 ALIAS(HCLK, NULL, "hclk"),
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| /linux/include/dt-bindings/clock/ |
| A D | s3c2410.h | 25 #define HCLK 5 macro
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| A D | s3c2412.h | 27 #define HCLK 7 macro
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| A D | s3c2443.h | 24 #define HCLK 5 macro
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| A D | samsung,s3c64xx-clock.h | 27 #define HCLK 8 macro
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| A D | stm32h7-clks.h | 3 #define HCLK 1 macro
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| /linux/include/video/ |
| A D | kyro.h | 33 u32 HCLK; /* Hor Clock */ member
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| /linux/drivers/mmc/host/ |
| A D | toshsd.c | 86 while (ios->clock < HCLK / div) in __toshsd_set_ios()
642 mmc->f_min = HCLK / 512; in toshsd_probe()
643 mmc->f_max = HCLK; in toshsd_probe()
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| A D | toshsd.h | 11 #define HCLK 33000000 /* 33 MHz (PCI clock) */ macro
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| /linux/Documentation/devicetree/bindings/mmc/ |
| A D | mtk-sd.yaml | 45 - description: HCLK which used for host (required).
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| A D | sdhci-msm.txt | 48 "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
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| /linux/arch/arm/boot/dts/ |
| A D | ste-nomadik-stn8815.dtsi | 226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
232 /* The PCLK domain uses HCLK right off */
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| /linux/drivers/video/fbdev/kyro/ |
| A D | fbdev.c | 506 par->HCLK = (1000000000 + (lineclock / 2)) / lineclock; in kyrofb_set_par()
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| /linux/drivers/clk/nxp/ |
| A D | clk-lpc32xx.c | 213 LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
1249 LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
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| /linux/drivers/clk/ |
| A D | clk-stm32h7.c | 517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre", in register_core_and_bus_clocks()
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