Searched refs:HHI_HDMI_CLK_CNTL (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/meson/ |
| A D | meson_vclk.c | 89 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
817 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
819 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
821 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
898 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
907 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
916 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
925 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
934 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
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| A D | meson_dw_hdmi.c | 108 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ macro
440 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in dw_hdmi_phy_init()
906 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_init()
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| /linux/drivers/clk/meson/ |
| A D | gxbb.h | 57 #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ macro
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| A D | meson8b.h | 45 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
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| A D | g12a.h | 74 #define HHI_HDMI_CLK_CNTL 0x1CC macro
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| A D | gxbb.c | 2279 .offset = HHI_HDMI_CLK_CNTL,
2374 .offset = HHI_HDMI_CLK_CNTL,
2390 .offset = HHI_HDMI_CLK_CNTL,
2405 .offset = HHI_HDMI_CLK_CNTL,
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| A D | meson8b.c | 1704 .offset = HHI_HDMI_CLK_CNTL,
1805 .offset = HHI_HDMI_CLK_CNTL,
1826 .offset = HHI_HDMI_CLK_CNTL,
1843 .offset = HHI_HDMI_CLK_CNTL,
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| A D | g12a.c | 3583 .offset = HHI_HDMI_CLK_CNTL,
3734 .offset = HHI_HDMI_CLK_CNTL,
3750 .offset = HHI_HDMI_CLK_CNTL,
3765 .offset = HHI_HDMI_CLK_CNTL,
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Completed in 26 milliseconds