Searched refs:HHI_VID_PLL_CLK_DIV (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/meson/ |
| A D | meson_vclk.c | 50 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
204 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
208 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
215 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
219 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
221 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
223 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
226 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
[all …]
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| /linux/drivers/clk/meson/ |
| A D | axg.h | 69 #define HHI_VID_PLL_CLK_DIV 0x1a0 macro
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| A D | gxbb.h | 52 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
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| A D | g12a.h | 69 #define HHI_VID_PLL_CLK_DIV 0x1A0 macro
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| A D | gxbb.c | 1740 .reg_off = HHI_VID_PLL_CLK_DIV,
1745 .reg_off = HHI_VID_PLL_CLK_DIV,
1783 .offset = HHI_VID_PLL_CLK_DIV,
1802 .offset = HHI_VID_PLL_CLK_DIV,
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| A D | g12a.c | 2640 .reg_off = HHI_VID_PLL_CLK_DIV,
2645 .reg_off = HHI_VID_PLL_CLK_DIV,
2666 .offset = HHI_VID_PLL_CLK_DIV,
2685 .offset = HHI_VID_PLL_CLK_DIV,
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