Searched refs:HHI_VIID_CLK_CNTL (Results 1 – 9 of 9) sorted by relevance
| /linux/drivers/gpu/drm/meson/ |
| A D | meson_vclk.c | 60 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
293 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); in meson_venci_cvbs_clock_config()
304 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
307 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
311 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); in meson_venci_cvbs_clock_config()
325 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
329 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
331 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
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| /linux/drivers/clk/meson/ |
| A D | axg.h | 52 #define HHI_VIID_CLK_CNTL 0x12c macro
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| A D | gxbb.h | 34 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
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| A D | meson8b.h | 28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
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| A D | axg.c | 1314 .offset = HHI_VIID_CLK_CNTL,
1405 .offset = HHI_VIID_CLK_CNTL,
1489 .offset = HHI_VIID_CLK_CNTL,
1503 .offset = HHI_VIID_CLK_CNTL,
1517 .offset = HHI_VIID_CLK_CNTL,
1531 .offset = HHI_VIID_CLK_CNTL,
1545 .offset = HHI_VIID_CLK_CNTL,
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| A D | g12a.h | 55 #define HHI_VIID_CLK_CNTL 0x12C macro
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| A D | gxbb.c | 1848 .offset = HHI_VIID_CLK_CNTL,
1944 .offset = HHI_VIID_CLK_CNTL,
2028 .offset = HHI_VIID_CLK_CNTL,
2042 .offset = HHI_VIID_CLK_CNTL,
2056 .offset = HHI_VIID_CLK_CNTL,
2070 .offset = HHI_VIID_CLK_CNTL,
2084 .offset = HHI_VIID_CLK_CNTL,
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| A D | g12a.c | 3157 .offset = HHI_VIID_CLK_CNTL,
3248 .offset = HHI_VIID_CLK_CNTL,
3332 .offset = HHI_VIID_CLK_CNTL,
3346 .offset = HHI_VIID_CLK_CNTL,
3360 .offset = HHI_VIID_CLK_CNTL,
3374 .offset = HHI_VIID_CLK_CNTL,
3388 .offset = HHI_VIID_CLK_CNTL,
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| A D | meson8b.c | 1420 .offset = HHI_VIID_CLK_CNTL,
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Completed in 25 milliseconds