1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* 3 * WF200 hardware interface definitions 4 * 5 * Copyright (c) 2018-2020, Silicon Laboratories Inc. 6 */ 7 8 #ifndef WFX_HIF_API_GENERAL_H 9 #define WFX_HIF_API_GENERAL_H 10 11 #ifdef __KERNEL__ 12 #include <linux/types.h> 13 #include <linux/if_ether.h> 14 #else 15 #include <net/ethernet.h> 16 #include <stdint.h> 17 #define __packed __attribute__((__packed__)) 18 #endif 19 20 #define HIF_ID_IS_INDICATION 0x80 21 #define HIF_COUNTER_MAX 7 22 23 struct hif_msg { 24 __le16 len; 25 u8 id; 26 u8 reserved:1; 27 u8 interface:2; 28 u8 seqnum:3; 29 u8 encrypted:2; 30 u8 body[]; 31 } __packed; 32 33 enum hif_general_requests_ids { 34 HIF_REQ_ID_CONFIGURATION = 0x09, 35 HIF_REQ_ID_CONTROL_GPIO = 0x26, 36 HIF_REQ_ID_SET_SL_MAC_KEY = 0x27, 37 HIF_REQ_ID_SL_EXCHANGE_PUB_KEYS = 0x28, 38 HIF_REQ_ID_SL_CONFIGURE = 0x29, 39 HIF_REQ_ID_PREVENT_ROLLBACK = 0x2a, 40 HIF_REQ_ID_PTA_SETTINGS = 0x2b, 41 HIF_REQ_ID_PTA_PRIORITY = 0x2c, 42 HIF_REQ_ID_PTA_STATE = 0x2d, 43 HIF_REQ_ID_SHUT_DOWN = 0x32, 44 }; 45 46 enum hif_general_confirmations_ids { 47 HIF_CNF_ID_CONFIGURATION = 0x09, 48 HIF_CNF_ID_CONTROL_GPIO = 0x26, 49 HIF_CNF_ID_SET_SL_MAC_KEY = 0x27, 50 HIF_CNF_ID_SL_EXCHANGE_PUB_KEYS = 0x28, 51 HIF_CNF_ID_SL_CONFIGURE = 0x29, 52 HIF_CNF_ID_PREVENT_ROLLBACK = 0x2a, 53 HIF_CNF_ID_PTA_SETTINGS = 0x2b, 54 HIF_CNF_ID_PTA_PRIORITY = 0x2c, 55 HIF_CNF_ID_PTA_STATE = 0x2d, 56 HIF_CNF_ID_SHUT_DOWN = 0x32, 57 }; 58 59 enum hif_general_indications_ids { 60 HIF_IND_ID_EXCEPTION = 0xe0, 61 HIF_IND_ID_STARTUP = 0xe1, 62 HIF_IND_ID_WAKEUP = 0xe2, 63 HIF_IND_ID_GENERIC = 0xe3, 64 HIF_IND_ID_ERROR = 0xe4, 65 HIF_IND_ID_SL_EXCHANGE_PUB_KEYS = 0xe5 66 }; 67 68 #define HIF_STATUS_SUCCESS (cpu_to_le32(0x0000)) 69 #define HIF_STATUS_FAIL (cpu_to_le32(0x0001)) 70 #define HIF_STATUS_INVALID_PARAMETER (cpu_to_le32(0x0002)) 71 #define HIF_STATUS_WARNING (cpu_to_le32(0x0003)) 72 #define HIF_STATUS_UNKNOWN_REQUEST (cpu_to_le32(0x0004)) 73 #define HIF_STATUS_RX_FAIL_DECRYPT (cpu_to_le32(0x0010)) 74 #define HIF_STATUS_RX_FAIL_MIC (cpu_to_le32(0x0011)) 75 #define HIF_STATUS_RX_FAIL_NO_KEY (cpu_to_le32(0x0012)) 76 #define HIF_STATUS_TX_FAIL_RETRIES (cpu_to_le32(0x0013)) 77 #define HIF_STATUS_TX_FAIL_TIMEOUT (cpu_to_le32(0x0014)) 78 #define HIF_STATUS_TX_FAIL_REQUEUE (cpu_to_le32(0x0015)) 79 #define HIF_STATUS_REFUSED (cpu_to_le32(0x0016)) 80 #define HIF_STATUS_BUSY (cpu_to_le32(0x0017)) 81 #define HIF_STATUS_SLK_SET_KEY_SUCCESS (cpu_to_le32(0x005A)) 82 #define HIF_STATUS_SLK_SET_KEY_ALREADY_BURNED (cpu_to_le32(0x006B)) 83 #define HIF_STATUS_SLK_SET_KEY_DISALLOWED_MODE (cpu_to_le32(0x007C)) 84 #define HIF_STATUS_SLK_SET_KEY_UNKNOWN_MODE (cpu_to_le32(0x008D)) 85 #define HIF_STATUS_SLK_NEGO_SUCCESS (cpu_to_le32(0x009E)) 86 #define HIF_STATUS_SLK_NEGO_FAILED (cpu_to_le32(0x00AF)) 87 #define HIF_STATUS_ROLLBACK_SUCCESS (cpu_to_le32(0x1234)) 88 #define HIF_STATUS_ROLLBACK_FAIL (cpu_to_le32(0x1256)) 89 90 enum hif_api_rate_index { 91 API_RATE_INDEX_B_1MBPS = 0, 92 API_RATE_INDEX_B_2MBPS = 1, 93 API_RATE_INDEX_B_5P5MBPS = 2, 94 API_RATE_INDEX_B_11MBPS = 3, 95 API_RATE_INDEX_PBCC_22MBPS = 4, 96 API_RATE_INDEX_PBCC_33MBPS = 5, 97 API_RATE_INDEX_G_6MBPS = 6, 98 API_RATE_INDEX_G_9MBPS = 7, 99 API_RATE_INDEX_G_12MBPS = 8, 100 API_RATE_INDEX_G_18MBPS = 9, 101 API_RATE_INDEX_G_24MBPS = 10, 102 API_RATE_INDEX_G_36MBPS = 11, 103 API_RATE_INDEX_G_48MBPS = 12, 104 API_RATE_INDEX_G_54MBPS = 13, 105 API_RATE_INDEX_N_6P5MBPS = 14, 106 API_RATE_INDEX_N_13MBPS = 15, 107 API_RATE_INDEX_N_19P5MBPS = 16, 108 API_RATE_INDEX_N_26MBPS = 17, 109 API_RATE_INDEX_N_39MBPS = 18, 110 API_RATE_INDEX_N_52MBPS = 19, 111 API_RATE_INDEX_N_58P5MBPS = 20, 112 API_RATE_INDEX_N_65MBPS = 21, 113 API_RATE_NUM_ENTRIES = 22 114 }; 115 116 struct hif_ind_startup { 117 /* As the others, this struct is interpreted as little endian by the 118 * device. However, this struct is also used by the driver. We prefer to 119 * declare it in native order and doing byte swap on reception. 120 */ 121 __le32 status; 122 u16 hardware_id; 123 u8 opn[14]; 124 u8 uid[8]; 125 u16 num_inp_ch_bufs; 126 u16 size_inp_ch_buf; 127 u8 num_links_ap; 128 u8 num_interfaces; 129 u8 mac_addr[2][ETH_ALEN]; 130 u8 api_version_minor; 131 u8 api_version_major; 132 u8 link_mode:2; 133 u8 reserved1:6; 134 u8 reserved2; 135 u8 reserved3; 136 u8 reserved4; 137 u8 firmware_build; 138 u8 firmware_minor; 139 u8 firmware_major; 140 u8 firmware_type; 141 u8 disabled_channel_list[2]; 142 u8 region_sel_mode:4; 143 u8 reserved5:4; 144 u8 phy1_region:3; 145 u8 phy0_region:3; 146 u8 otp_phy_ver:2; 147 u32 supported_rate_mask; 148 u8 firmware_label[128]; 149 } __packed; 150 151 struct hif_ind_wakeup { 152 } __packed; 153 154 struct hif_req_configuration { 155 __le16 length; 156 u8 pds_data[]; 157 } __packed; 158 159 struct hif_cnf_configuration { 160 __le32 status; 161 } __packed; 162 163 enum hif_gpio_mode { 164 HIF_GPIO_MODE_D0 = 0x0, 165 HIF_GPIO_MODE_D1 = 0x1, 166 HIF_GPIO_MODE_OD0 = 0x2, 167 HIF_GPIO_MODE_OD1 = 0x3, 168 HIF_GPIO_MODE_TRISTATE = 0x4, 169 HIF_GPIO_MODE_TOGGLE = 0x5, 170 HIF_GPIO_MODE_READ = 0x6 171 }; 172 173 struct hif_req_control_gpio { 174 u8 gpio_label; 175 u8 gpio_mode; 176 } __packed; 177 178 struct hif_cnf_control_gpio { 179 __le32 status; 180 __le32 value; 181 } __packed; 182 183 enum hif_generic_indication_type { 184 HIF_GENERIC_INDICATION_TYPE_RAW = 0x0, 185 HIF_GENERIC_INDICATION_TYPE_STRING = 0x1, 186 HIF_GENERIC_INDICATION_TYPE_RX_STATS = 0x2, 187 HIF_GENERIC_INDICATION_TYPE_TX_POWER_LOOP_INFO = 0x3, 188 }; 189 190 struct hif_rx_stats { 191 __le32 nb_rx_frame; 192 __le32 nb_crc_frame; 193 __le32 per_total; 194 __le32 throughput; 195 __le32 nb_rx_by_rate[API_RATE_NUM_ENTRIES]; 196 __le16 per[API_RATE_NUM_ENTRIES]; 197 __le16 snr[API_RATE_NUM_ENTRIES]; /* signed value */ 198 __le16 rssi[API_RATE_NUM_ENTRIES]; /* signed value */ 199 __le16 cfo[API_RATE_NUM_ENTRIES]; /* signed value */ 200 __le32 date; 201 __le32 pwr_clk_freq; 202 u8 is_ext_pwr_clk; 203 s8 current_temp; 204 } __packed; 205 206 struct hif_tx_power_loop_info { 207 __le16 tx_gain_dig; 208 __le16 tx_gain_pa; 209 __le16 target_pout; /* signed value */ 210 __le16 p_estimation; /* signed value */ 211 __le16 vpdet; 212 u8 measurement_index; 213 u8 reserved; 214 } __packed; 215 216 struct hif_ind_generic { 217 __le32 type; 218 union { 219 struct hif_rx_stats rx_stats; 220 struct hif_tx_power_loop_info tx_power_loop_info; 221 } data; 222 } __packed; 223 224 enum hif_error { 225 HIF_ERROR_FIRMWARE_ROLLBACK = 0x00, 226 HIF_ERROR_FIRMWARE_DEBUG_ENABLED = 0x01, 227 HIF_ERROR_SLK_OUTDATED_SESSION_KEY = 0x02, 228 HIF_ERROR_SLK_SESSION_KEY = 0x03, 229 HIF_ERROR_OOR_VOLTAGE = 0x04, 230 HIF_ERROR_PDS_PAYLOAD = 0x05, 231 HIF_ERROR_OOR_TEMPERATURE = 0x06, 232 HIF_ERROR_SLK_REQ_DURING_KEY_EXCHANGE = 0x07, 233 HIF_ERROR_SLK_MULTI_TX_UNSUPPORTED = 0x08, 234 HIF_ERROR_SLK_OVERFLOW = 0x09, 235 HIF_ERROR_SLK_DECRYPTION = 0x0a, 236 HIF_ERROR_SLK_WRONG_ENCRYPTION_STATE = 0x0b, 237 HIF_ERROR_HIF_BUS_FREQUENCY_TOO_LOW = 0x0c, 238 HIF_ERROR_HIF_RX_DATA_TOO_LARGE = 0x0e, 239 HIF_ERROR_HIF_TX_QUEUE_FULL = 0x0d, 240 HIF_ERROR_HIF_BUS = 0x0f, 241 HIF_ERROR_PDS_TESTFEATURE = 0x10, 242 HIF_ERROR_SLK_UNCONFIGURED = 0x11, 243 }; 244 245 struct hif_ind_error { 246 __le32 type; 247 u8 data[]; 248 } __packed; 249 250 struct hif_ind_exception { 251 __le32 type; 252 u8 data[]; 253 } __packed; 254 255 enum hif_secure_link_state { 256 SEC_LINK_UNAVAILABLE = 0x0, 257 SEC_LINK_RESERVED = 0x1, 258 SEC_LINK_EVAL = 0x2, 259 SEC_LINK_ENFORCED = 0x3 260 }; 261 262 #endif 263