| /linux/Documentation/scsi/ |
| A D | scsi-parameters.rst | 19 advansys= [HW,SCSI]
22 aha152x= [HW,SCSI]
25 aha1542= [HW,SCSI]
28 aic7xxx= [HW,SCSI]
31 aic79xx= [HW,SCSI]
34 atascsi= [HW,SCSI]
37 BusLogic= [HW,SCSI]
41 gvp11= [HW,SCSI]
46 mac5380= [HW,SCSI]
57 NCR_D700= [HW,SCSI]
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| /linux/Documentation/networking/device_drivers/ethernet/huawei/ |
| A D | hinic.rst | 35 specific HW details about HW data structure formats.
43 HW Interface:
49 Configuration Status Registers Area that describes the HW Registers on the
63 card by AEQs. Also set the addresses of the IO CMDQs in HW.
78 used to set the QPs addresses in HW. The commands completion events are
87 HW device:
90 HW device - de/constructs the HW Interface, the MGMT components on the
101 Port Commands - Send commands to the HW device for port management
104 Tx Queues - Logical Tx Queues that use the HW Send Queues for transmit.
105 The Logical Tx queue is not dependent on the format of the HW Send Queue.
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| /linux/Documentation/watchdog/ |
| A D | mlx-wdt.rst | 13 There are 2 types of HW watchdog implementations.
16 Actual HW timeout can be defined as a power of 2 msec.
22 Actual HW timeout is defined in sec. and it's the same as
31 Type 1 HW watchdog implementation exist in old systems and
32 all new systems have type 2 HW watchdog.
33 Two types of HW implementation have also different register map.
35 Type 3 HW watchdog implementation can exist on all Mellanox systems
54 This mlx-wdt driver supports both HW watchdog implementations.
65 Access to HW registers is performed through a generic regmap interface.
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| /linux/Documentation/networking/dsa/ |
| A D | lan9303.rst | 21 interfaces (which is the default state of a DSA device). Due to HW limitations,
22 no HW MAC learning takes place in this mode.
24 When both user ports are joined to the same bridge, the normal HW MAC learning
25 is enabled. This means that unicast traffic is forwarded in HW. Broadcast and
26 multicast is flooded in HW. STP is also supported in this mode. The driver
37 - The HW does not support VLAN-specific fdb entries
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| /linux/Documentation/translations/zh_CN/infiniband/ |
| A D | opa_vnic.rst | 117 依赖于HW的VNIC功能是HFI1驱动的一部分。它实现了分配和释放OPA_VNIC RDMA
118 netdev的动作。它涉及VNIC功能的HW资源分配/管理。它与网络堆栈接口并实现所
120 并提供对它们的HW访问。在将数据包向上传递到网络堆栈之前，它把Omni-Path头
126 RDMA netdev设备。它在需要时覆盖由依赖HW的VNIC驱动设置的net_device_ops函数，
129 RDMA netdev控制操作将任何控制信息传递给依赖于HW的驱动程序::
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| /linux/Documentation/ABI/testing/ |
| A D | sysfs-bus-coresight-devices-etb10 | 27 2. The value is read directly from HW register RDP, 0x004.
34 is read directly from HW register STS, 0x00C.
42 interface. The value is read directly from HW register RRP,
52 from HW register RWP, 0x018.
59 read directly from HW register TRG, 0x01C.
66 is read directly from HW register CTL, 0x020.
73 register. The value is read directly from HW register FFSR,
81 register. The value is read directly from HW register FFCR,
|
| A D | sysfs-bus-coresight-devices-tmc | 15 The value is read directly from HW register RSZ, 0x004.
22 is read directly from HW register STS, 0x00C.
30 interface. The value is read directly from HW register RRP,
40 from HW register RWP, 0x018.
47 read directly from HW register TRG, 0x01C.
54 is read directly from HW register CTL, 0x020.
61 register. The value is read directly from HW register FFSR,
69 register. The value is read directly from HW register FFCR,
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| A D | sysfs-bus-coresight-devices-etm4x | 337 The value it taken directly from the HW.
344 (0x310). The value is taken directly from the HW.
380 from the HW.
435 The value is taken directly from the HW.
442 The value is taken directly from the HW.
459 The value is taken directly from the HW.
466 The value is taken directly from the HW.
473 The value is taken directly from the HW.
502 the HW.
510 from the HW.
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| /linux/Documentation/devicetree/bindings/regulator/ |
| A D | rohm,bd71815-regulator.yaml | 55 PMIC "RUN" state voltage in uV when PMIC HW states are used. See
75 PMIC "SUSPEND" state voltage in uV when PMIC HW states are used. See
84 PMIC "LPSR" state voltage in uV when PMIC HW states are used. See
93 # (LPSR/SUSPEND). The voltage is automatically changed when HW
95 # buck voltages to not be toggled by HW state. Enable status may still
96 # be toggled by state changes depending on HW default settings.
105 # for each of the HW states (RUN/SNVS/SUSPEND/LPSR). HW defaults can
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| /linux/Documentation/devicetree/bindings/clock/ti/ |
| A D | interface.txt | 19 "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
21 "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
22 "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
23 "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
24 "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
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| /linux/Documentation/driver-api/iio/ |
| A D | hw-consumer.rst | 2 HW consumer
6 The Industrial I/O HW consumer offers a way to bond these IIO devices without
18 HW consumer setup
22 A typical IIO HW consumer setup looks like this::
|
| /linux/Documentation/infiniband/ |
| A D | opa_vnic.rst | 104 OPA VNIC functionality has a HW dependent component and a HW
112 The HW dependent VNIC functionality is part of the HFI1 driver. It
114 It involves HW resource allocation/management for VNIC functionality.
117 packets in the transmit path and provides HW access to them. It strips
121 The OPA VNIC module implements the HW independent VNIC functionality.
127 set by HW dependent VNIC driver where required to accommodate any control
131 interface. It also passes any control information to the HW dependent driver
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| /linux/drivers/crypto/keembay/ |
| A D | Kconfig | 2 tristate "Support for Intel Keem Bay OCS AES/SM4 HW acceleration"
12 Provides HW acceleration for the following transformations:
20 bool "Support for Intel Keem Bay OCS AES/SM4 ECB HW acceleration"
31 bool "Support for Intel Keem Bay OCS AES/SM4 CTS HW acceleration"
43 tristate "Support for Intel Keem Bay OCS ECC HW acceleration"
62 tristate "Support for Intel Keem Bay OCS HCU HW acceleration"
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/en/ |
| A D | port_buffer.c | 68 mlx5e_dbg(HW, priv, "buffer %d: size=%d, xon=%d, xoff=%d, epsb=%d, lossy=%d\n", i, in mlx5e_port_query_buffer()
81 mlx5e_dbg(HW, priv, "total buffer size=%d, spare buffer size=%d\n", in mlx5e_port_query_buffer()
144 mlx5e_dbg(HW, priv, "%s: xoff=%d\n", __func__, xoff); in calculate_xoff()
281 mlx5e_dbg(HW, priv, "%s: change=%x\n", __func__, change); in mlx5e_port_manual_buffer_config()
320 mlx5e_dbg(HW, priv, "%s: buffer[%d]=%d\n", __func__, i, buffer_size[i]); in mlx5e_port_manual_buffer_config()
322 mlx5e_dbg(HW, priv, "%s: lossless buffer[%d] size cannot be zero\n", in mlx5e_port_manual_buffer_config()
331 mlx5e_dbg(HW, priv, "%s: total buffer requested=%d\n", __func__, total_used); in mlx5e_port_manual_buffer_config()
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| /linux/Documentation/devicetree/bindings/iommu/ |
| A D | mediatek,iommu.yaml | 14 this M4U have two generations of HW architecture. Generation one uses flat
52 As above, The Multimedia HW will go through SMI and M4U while it
53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
55 HW should go though the m4u for translation or bypass it and talk
59 Normally we specify a local arbiter(larb) for each multimedia HW
62 video decode local arbiter, all these ports are according to the video HW.
112 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
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| /linux/Documentation/devicetree/bindings/dma/ |
| A D | qcom_hidma_mgmt.txt | 7 Each HIDMA HW instance consists of multiple DMA channels. These channels
37 Once a reset is applied to the HW, HW starts a timer for reset operation
38 to confirm. If reset is not completed within this time, HW reports reset
50 - compatible: must contain "qcom,hidma-1.0" for initial HW or
51 "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
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| /linux/net/tls/ |
| A D | Kconfig | 21 bool "Transport Layer Security HW offload"
27 Enable kernel support for HW offload of the TLS protocol.
36 Enable kernel support for legacy HW offload of the TLS protocol,
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| /linux/Documentation/networking/device_drivers/ethernet/stmicro/ |
| A D | stmmac.rst | 159 This parameter changes the default HW FIFO Threshold control value.
263 checks to the HW using MAC and PHY loopback mechanisms::
328 PHYLIB stuff. In fact, the HW provides a subset of extended registers to
372 7) HW uses the GMAC core::
380 9) Core is able to perform TX Checksum and/or RX Checksum in HW::
470 30) HW uses GMAC>4 cores::
474 31) HW is sun8i based::
494 36) HW uses XGMAC>2.10 cores::
664 HW Capabilities
669 understand if EEE, HW csum, PTP, enhanced descriptor etc are actually
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| /linux/Documentation/virt/kvm/devices/ |
| A D | xive.rst | 21 The KVM device exposes different MMIO ranges of the XIVE HW which
52 interrupts are from a different HW controller (PHB4) and the ESB
56 kvmppc_xive_clr_mapped() are called when the device HW irqs are
60 The handler will insert the ESB page corresponding to the HW
119 -ENXIO Could not allocate underlying HW interrupt
147 underlying HW interrupt failed
192 -EIO Configuration of the underlying HW failed
211 called the NVT. When a VP is not dispatched on a HW processor
212 thread, this structure can be updated by HW if the VP is the target
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| /linux/drivers/gpu/drm/sti/ |
| A D | NOTES | 3 The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
19 - The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
20 Note that some stiH drivers support only a subset of thee HW IP.
37 2. DRM / HW mapping
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| /linux/Documentation/x86/ |
| A D | tsx_async_abort.rst | 69 …0 0 0 HW default Yes Same as MDS Same as MDS
71 …0 1 0 HW default No Need ucode update Need ucode up…
84 … 0 0 0 HW default Yes Same as MDS Same as MDS
86 …0 1 0 HW default No Need ucode update Need ucode up…
99 …0 0 0 HW default Yes Same as MDS Same as MDS
101 …0 1 0 HW default No Need ucode update Need ucode up…
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| /linux/Documentation/devicetree/bindings/reset/ |
| A D | reset.txt | 21 in hardware for a reset signal to affect multiple logically separate HW blocks
23 the DT node of each affected HW block, since if activated, an unrelated block
26 children of the bus are affected by the reset signal, or an individual HW
28 appropriate software access to the reset signals in order to manage the HW,
29 rather than to slavishly enumerate the reset signal that affects each HW
|
| /linux/Documentation/powerpc/ |
| A D | cpu_families.rst | 173 - e6500 adds HW loaded indirect TLB entries.
206 | e6500 (HW TLB) (Multithreaded) |
213 - Book3E, software loaded TLB + HW loaded indirect TLB entries.
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| A D | mediatek,smi-common.yaml | 16 MediaTek SMI have two generations of HW architecture, here is the list
56 apb and smi are mandatory. the async is only for generation 1 smi HW.
83 - if: # only for gen1 HW
124 - if: # for gen2 HW that have gals
147 else: # for gen2 HW that don't have gals
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| /linux/Documentation/devicetree/bindings/gpio/ |
| A D | nvidia,tegra186-gpio.txt | 11 package balls is under the control of a separate pin controller HW block. Two
30 Tegra HW documentation describes a unified naming convention for all GPIOs
44 matches the HW documentation. The values chosen for the names are alphabetically
46 IDs and HW register offsets using a lookup table.
51 of the number of ports it implements. Note that the HW documentation refers to
52 both the overall controller HW module and the sets-of-ports as "controllers".
91 The interrupt outputs from the HW block, one per set of ports, in the
92 order the HW manual describes them. The number of entries required varies
|