Searched refs:I915_MAX_PIPES (Results 1 – 16 of 16) sorted by relevance
25 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];40 unsigned int data_rate[I915_MAX_PIPES];41 u8 num_active_planes[I915_MAX_PIPES];
43 int min_cdclk[I915_MAX_PIPES];45 u8 min_voltage_level[I915_MAX_PIPES];
313 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
93 I915_MAX_PIPES = _PIPE_EDP enumerator350 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
462 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init()
1590 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
9559 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_commit_modeset_enables()9596 entries, I915_MAX_PIPES, pipe)) in skl_commit_modeset_enables()9664 entries, I915_MAX_PIPES, pipe)); in skl_commit_modeset_enables()9789 u64 put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()
77 struct skl_ddb_entry ddb[I915_MAX_PIPES];78 unsigned int weight[I915_MAX_PIPES];79 u8 slices[I915_MAX_PIPES];
217 int cursor_offsets[I915_MAX_PIPES];240 u8 num_sprites[I915_MAX_PIPES];241 u8 num_scalers[I915_MAX_PIPES];
916 u32 de_irq_mask[I915_MAX_PIPES];918 u32 pipestat_irq_mask[I915_MAX_PIPES];1019 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];1020 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];1107 u32 chv_dpll_md[I915_MAX_PIPES];1231 struct intel_encoder *av_enc_map[I915_MAX_PIPES];1312 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1430 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument1496 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) in i8xx_pipestat_irq_handler() argument1513 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument1537 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument1564 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument1664 u32 pipe_stats[I915_MAX_PIPES] = {}; in valleyview_irq_handler()1751 u32 pipe_stats[I915_MAX_PIPES] = {}; in cherryview_irq_handler()4052 u32 pipe_stats[I915_MAX_PIPES] = {}; in i8xx_irq_handler()4155 u32 pipe_stats[I915_MAX_PIPES] = {}; in i915_irq_handler()4301 u32 pipe_stats[I915_MAX_PIPES] = {}; in i965_irq_handler()
4408 u8 dbuf_mask[I915_MAX_PIPES];
186 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()210 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()341 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_cursor_plane()420 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_sprite_plane()
163 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
120 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
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