1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * IMX pinmux core definitions 4 * 5 * Copyright (C) 2012 Freescale Semiconductor, Inc. 6 * Copyright (C) 2012 Linaro Ltd. 7 * 8 * Author: Dong Aisheng <dong.aisheng@linaro.org> 9 */ 10 11 #ifndef __DRIVERS_PINCTRL_IMX_H 12 #define __DRIVERS_PINCTRL_IMX_H 13 14 #include <linux/pinctrl/pinconf-generic.h> 15 #include <linux/pinctrl/pinmux.h> 16 17 struct platform_device; 18 19 extern struct pinmux_ops imx_pmx_ops; 20 extern const struct dev_pm_ops imx_pinctrl_pm_ops; 21 22 /** 23 * struct imx_pin_mmio - MMIO pin configurations 24 * @mux_mode: the mux mode for this pin. 25 * @input_reg: the select input register offset for this pin if any 26 * 0 if no select input setting needed. 27 * @input_val: the select input value for this pin. 28 * @configs: the config for this pin. 29 */ 30 struct imx_pin_mmio { 31 unsigned int mux_mode; 32 u16 input_reg; 33 unsigned int input_val; 34 unsigned long config; 35 }; 36 37 /** 38 * struct imx_pin_scu - SCU pin configurations 39 * @mux: the mux mode for this pin. 40 * @configs: the config for this pin. 41 */ 42 struct imx_pin_scu { 43 unsigned int mux_mode; 44 unsigned long config; 45 }; 46 47 /** 48 * struct imx_pin - describes a single i.MX pin 49 * @pin: the pin_id of this pin 50 * @conf: config type of this pin, either mmio or scu 51 */ 52 struct imx_pin { 53 unsigned int pin; 54 union { 55 struct imx_pin_mmio mmio; 56 struct imx_pin_scu scu; 57 } conf; 58 }; 59 60 /** 61 * struct imx_pin_reg - describe a pin reg map 62 * @mux_reg: mux register offset 63 * @conf_reg: config register offset 64 */ 65 struct imx_pin_reg { 66 s16 mux_reg; 67 s16 conf_reg; 68 }; 69 70 /* decode a generic config into raw register value */ 71 struct imx_cfg_params_decode { 72 enum pin_config_param param; 73 u32 mask; 74 u8 shift; 75 bool invert; 76 }; 77 78 /** 79 * @dev: a pointer back to containing device 80 * @base: the offset to the controller in virtual memory 81 */ 82 struct imx_pinctrl { 83 struct device *dev; 84 struct pinctrl_dev *pctl; 85 void __iomem *base; 86 void __iomem *input_sel_base; 87 const struct imx_pinctrl_soc_info *info; 88 struct imx_pin_reg *pin_regs; 89 unsigned int group_index; 90 struct mutex mutex; 91 }; 92 93 struct imx_pinctrl_soc_info { 94 const struct pinctrl_pin_desc *pins; 95 unsigned int npins; 96 unsigned int flags; 97 const char *gpr_compatible; 98 99 /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */ 100 unsigned int mux_mask; 101 u8 mux_shift; 102 103 /* generic pinconf */ 104 bool generic_pinconf; 105 const struct pinconf_generic_params *custom_params; 106 unsigned int num_custom_params; 107 const struct imx_cfg_params_decode *decodes; 108 unsigned int num_decodes; 109 void (*fixup)(unsigned long *configs, unsigned int num_configs, 110 u32 *raw_config); 111 112 int (*gpio_set_direction)(struct pinctrl_dev *pctldev, 113 struct pinctrl_gpio_range *range, 114 unsigned offset, 115 bool input); 116 int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id, 117 unsigned long *config); 118 int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id, 119 unsigned long *configs, unsigned int num_configs); 120 void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl, 121 unsigned int *pin_id, struct imx_pin *pin, 122 const __be32 **list_p); 123 }; 124 125 #define IMX_CFG_PARAMS_DECODE(p, m, o) \ 126 { .param = p, .mask = m, .shift = o, .invert = false, } 127 128 #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ 129 { .param = p, .mask = m, .shift = o, .invert = true, } 130 131 #define SHARE_MUX_CONF_REG BIT(0) 132 #define ZERO_OFFSET_VALID BIT(1) 133 #define IMX_USE_SCU BIT(2) 134 135 #define NO_MUX 0x0 136 #define NO_PAD 0x0 137 138 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) 139 140 #define PAD_CTL_MASK(len) ((1 << len) - 1) 141 #define IMX_MUX_MASK 0x7 142 #define IOMUXC_CONFIG_SION (0x1 << 4) 143 144 int imx_pinctrl_probe(struct platform_device *pdev, 145 const struct imx_pinctrl_soc_info *info); 146 147 #define BM_PAD_CTL_GP_ENABLE BIT(30) 148 #define BM_PAD_CTL_IFMUX_ENABLE BIT(31) 149 #define BP_PAD_CTL_IFMUX 27 150 151 int imx_pinctrl_sc_ipc_init(struct platform_device *pdev); 152 int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id, 153 unsigned long *config); 154 int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, 155 unsigned long *configs, unsigned num_configs); 156 void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, 157 unsigned int *pin_id, struct imx_pin *pin, 158 const __be32 **list_p); 159 #endif /* __DRIVERS_PINCTRL_IMX_H */ 160