Searched refs:INTERLACE (Results 1 – 23 of 23) sorted by relevance
51 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()262 if (patched_crtc_timing.flags.INTERLACE == 1) in optc1_program_timing()268 if (patched_crtc_timing.flags.INTERLACE == 1) in optc1_program_timing()360 if (patched_crtc_timing.flags.INTERLACE == 1) { in optc1_set_vtg_params()591 if (timing->flags.INTERLACE == 1) in optc1_validate_timing()611 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; in optc1_validate_timing()
272 if (hw_crtc_timing.flags.INTERLACE) { in enc1_stream_encoder_dp_set_stream_attribute()
3541 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()3562 interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1; in dcn10_get_vupdate_offset_from_vsync()
117 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; in optc201_validate_timing()
190 uint32_t INTERLACE:1; member
119 uint32_t INTERLACE:1; member
171 # define INTERLACE BIT(26) macro
69 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()336 if (patched_crtc_timing.flags.INTERLACE == 1) in dce110_timing_generator_program_timing_generator()337 bp_params.flags.INTERLACE = 1; in dce110_timing_generator_program_timing_generator()1136 if (timing->flags.INTERLACE == 1) in dce110_timing_generator_validate_timing()
377 timing->flags.INTERLACE, in dce110_timing_generator_v_program_blanking()
1368 stream->timing.flags.INTERLACE;
676 uint32_t INTERLACE :1; member
235 uint32_t INTERLACE :1; member
216 if (hw_crtc_timing.flags.INTERLACE) { in dcn31_hpo_dp_stream_enc_set_stream_attribute()
630 if (bp_params->flags.INTERLACE) { in set_crtc_using_dtd_timing_v3()
1864 if (bp_params->flags.INTERLACE) { in set_crtc_timing_v1()1943 if (bp_params->flags.INTERLACE) { in set_crtc_using_dtd_timing_v3()
1282 info->lcd_timing.misc_info.INTERLACE = in get_embedded_panel_info_v1_2()1400 info->lcd_timing.misc_info.INTERLACE = in get_embedded_panel_info_v1_3()
1182 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); in get_embedded_panel_info_v2_1()
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
295 if (hw_crtc_timing.flags.INTERLACE) { in dce110_stream_encoder_dp_set_stream_attribute()
1242 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); in dcn_validate_bandwidth()1248 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); in dcn_validate_bandwidth()
599 fbiinit5 |= INTERLACE; in sstfb_set_par()
653 bool interlace = stream->timing.flags.INTERLACE; in dcn20_enable_stream_timing()
2086 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; in dcn20_populate_dml_pipes_from_context()
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