| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| A D | irq_service_dcn201.c | 160 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
176 IRQ_REG_ENTRY(HPD, reg_num,\
185 IRQ_REG_ENTRY(HPD, reg_num,\
193 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
201 IRQ_REG_ENTRY(OTG, reg_num,\
212 IRQ_REG_ENTRY(OTG, reg_num,\
219 IRQ_REG_ENTRY(OTG, reg_num,\
227 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| A D | irq_service_dcn10.c | 203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
219 IRQ_REG_ENTRY(HPD, reg_num,\
228 IRQ_REG_ENTRY(HPD, reg_num,\
236 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
247 IRQ_REG_ENTRY(OTG, reg_num,\
255 IRQ_REG_ENTRY(OTG, reg_num,\
263 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| A D | irq_service_dce120.c | 105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
121 IRQ_REG_ENTRY(HPD, reg_num,\
130 IRQ_REG_ENTRY(HPD, reg_num,\
138 IRQ_REG_ENTRY(DCP, reg_num, \
147 IRQ_REG_ENTRY(CRTC, reg_num,\
155 IRQ_REG_ENTRY(CRTC, reg_num,\
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| A D | irq_service_dcn303.c | 110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
125 IRQ_REG_ENTRY(HPD, reg_num,\
134 IRQ_REG_ENTRY(HPD, reg_num,\
142 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
153 IRQ_REG_ENTRY(OTG, reg_num,\
161 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| A D | irq_service_dcn21.c | 241 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
271 IRQ_REG_ENTRY(HPD, reg_num,\
280 IRQ_REG_ENTRY(HPD, reg_num,\
288 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
296 IRQ_REG_ENTRY(OTG, reg_num,\
307 IRQ_REG_ENTRY(OTG, reg_num,\
315 IRQ_REG_ENTRY(OTG, reg_num,\
323 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| A D | irq_service_dcn20.c | 230 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
248 IRQ_REG_ENTRY(HPD, reg_num,\
257 IRQ_REG_ENTRY(HPD, reg_num,\
265 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
276 IRQ_REG_ENTRY(OTG, reg_num,\
284 IRQ_REG_ENTRY(OTG, reg_num,\
292 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| A D | irq_service_dcn30.c | 222 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
252 IRQ_REG_ENTRY(HPD, reg_num,\
261 IRQ_REG_ENTRY(HPD, reg_num,\
269 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
280 IRQ_REG_ENTRY(OTG, reg_num,\
288 IRQ_REG_ENTRY(OTG, reg_num,\
296 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| A D | irq_service_dcn302.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
229 IRQ_REG_ENTRY(HPD, reg_num,\
238 IRQ_REG_ENTRY(HPD, reg_num,\
246 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
257 IRQ_REG_ENTRY(OTG, reg_num,\
265 IRQ_REG_ENTRY(OTG, reg_num,\
273 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| A D | irq_service_dcn31.c | 209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
239 IRQ_REG_ENTRY(HPD, reg_num,\
248 IRQ_REG_ENTRY(HPD, reg_num,\
256 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
267 IRQ_REG_ENTRY(OTG, reg_num,\
275 IRQ_REG_ENTRY(OTG, reg_num,\
283 IRQ_REG_ENTRY(OTG, reg_num,\
|