Searched refs:JZ4760_CLK_PLL1 (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/clk/ingenic/ |
| A D | jz4760-cgu.c | 118 [JZ4760_CLK_PLL1] = {
208 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
215 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
222 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
240 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
251 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
259 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
266 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
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| /linux/include/dt-bindings/clock/ |
| A D | ingenic,jz4760-cgu.h | 13 #define JZ4760_CLK_PLL1 4 macro
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