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/linux/Documentation/devicetree/bindings/sound/
A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
86 - description: Parent for CPB_McASP auxclk (for 48KHz)
87 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
89 - description: Parent for CPB_SCKI clock (for 48KHz)
90 - description: Parent for CPB_SCKI clock (for 44.1KHz)
113 - description: Parent for CPB_McASP auxclk (for 48KHz)
[all …]
A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
83 - description: Parent for IVI_McASP auxclk (for 44.1KHz)
85 - description: Parent for IVI_SCKI clock (for 48KHz)
[all …]
A Dgtm601.txt6 "broadmobi,bm818" = 48KHz stereo
/linux/arch/arm/plat-omap/
A DKconfig72 timer provides more intra-tick resolution than the 32KHz timer,
76 bool "Use 32KHz timer"
80 Select this option if you want to enable the OMAP 32KHz timer.
82 support for no tick during idle. The 32KHz timer provides less
83 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
/linux/Documentation/ABI/testing/
A Dsysfs-class-rtc-rtc0-device-rtc_calibration7 calibrate the AB8500.s 32KHz Real Time Clock.
12 30.5 micro-seconds (half-parts-per-million of the 32KHz clock)
/linux/Documentation/devicetree/bindings/regulator/
A Drichtek,rt6245-regulator.yaml63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
/linux/Documentation/devicetree/bindings/i2c/
A Di2c-ocores.txt25 Defaults to 100 KHz when the property is not specified
37 frequency is fixed at 100 KHz.
69 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
/linux/Documentation/devicetree/bindings/clock/
A Dclk-palmas-clk32kg-clocks.txt1 * Palmas 32KHz clocks *
3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
A Dsamsung,s2mps11.yaml17 outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs.
/linux/drivers/cpufreq/
A Dscmi-cpufreq.c99 scmi_get_cpu_power(unsigned long *power, unsigned long *KHz, in scmi_get_cpu_power() argument
110 Hz = *KHz * 1000; in scmi_get_cpu_power()
116 *KHz = Hz / 1000; in scmi_get_cpu_power()
A Dmediatek-cpufreq-hw.c53 unsigned long *KHz, struct device *cpu_dev) in mtk_cpufreq_get_cpu_power() argument
66 if (data->table[i].frequency < *KHz) in mtk_cpufreq_get_cpu_power()
71 *KHz = data->table[i].frequency; in mtk_cpufreq_get_cpu_power()
/linux/drivers/media/dvb-frontends/
A Ds5h1411.c376 static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz) in s5h1411_set_if_freq() argument
380 dprintk("%s(%d KHz)\n", __func__, KHz); in s5h1411_set_if_freq()
382 switch (KHz) { in s5h1411_set_if_freq()
400 __func__, KHz); in s5h1411_set_if_freq()
410 state->if_freq = KHz; in s5h1411_set_if_freq()
A Ds5h1409.c353 static int s5h1409_set_if_freq(struct dvb_frontend *fe, int KHz) in s5h1409_set_if_freq() argument
357 dprintk("%s(%d KHz)\n", __func__, KHz); in s5h1409_set_if_freq()
359 switch (KHz) { in s5h1409_set_if_freq()
373 state->if_freq = KHz; in s5h1409_set_if_freq()
/linux/Documentation/devicetree/bindings/mfd/
A Dmax77620.txt36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
/linux/arch/arm/boot/dts/
A Dsun5i-reference-design-tablet.dtsi88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
/linux/drivers/clk/pxa/
A Dclk-pxa27x.c21 #define KHz 1000 macro
122 return (unsigned int)clks[0] / KHz; in pxa27x_get_clk_frequency_khz()
316 32768 * KHz)); in pxa27x_register_plls()
A Dclk-pxa25x.c23 #define KHz 1000 macro
118 return (unsigned int)clks[0] / KHz; in pxa25x_get_clk_frequency_khz()
A Dclk-pxa3xx.c23 #define KHz 1000 macro
78 return (unsigned int)clks[0] / KHz; in pxa3xx_get_clk_frequency_khz()
/linux/Documentation/devicetree/bindings/timer/
A Dspreadtrum,sprd-timer.txt12 - clocks: The phandle to the source clock (usually a 32.768 KHz fixed clock).
/linux/Documentation/devicetree/bindings/rtc/
A Datmel,at91sam9-rtc.txt9 - clocks: should contain the 32 KHz slow clk that will drive the RTT block.
/linux/Documentation/devicetree/bindings/media/
A Dimg-ir-rev1.txt16 1st: Core clock (defaults to 32.768KHz if omitted).
/linux/drivers/gpu/drm/i915/display/
A Dintel_backlight.c1029 return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(dev_priv)->rawclk_freq), in cnp_hz_to_pwm()
1038 return DIV_ROUND_CLOSEST(KHz(19200), pwm_freq_hz); in bxt_hz_to_pwm()
1091 return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(dev_priv)->rawclk_freq), in pch_hz_to_pwm()
1109 clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq); in i9xx_hz_to_pwm()
1111 clock = KHz(dev_priv->cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1127 clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq); in i965_hz_to_pwm()
1129 clock = KHz(dev_priv->cdclk.hw.cdclk); in i965_hz_to_pwm()
1146 clock = KHz(19200); in vlv_hz_to_pwm()
1151 clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq); in vlv_hz_to_pwm()
/linux/Documentation/misc-devices/
A Dics932s401.rst27 All frequencies are reported in KHz.
/linux/Documentation/userspace-api/media/dvb/
A Dfe-diseqc-send-burst.rst13 FE_DISEQC_SEND_BURST - Sends a 22KHz tone burst for 2x1 mini DiSEqC satellite selection.
/linux/Documentation/devicetree/bindings/net/wireless/
A Dieee80211.yaml25 List of supported frequency ranges in KHz. This can be used for devices

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