| /linux/arch/alpha/lib/ |
| A D | ev67-strncat.S | 58 bsr $23, __stxncpy # L0 :/* Now do the append. */
65 ret # L0 :
81 ret # L0 :
87 ret # L0 :
93 ret # L0 :
|
| A D | ev6-memset.S | 214 ret $31,($26),1 # L0 :
231 ret $31,($26),1 # L0 :
392 ret $31,($26),1 # L0 :
409 ret $31,($26),1 # L0 :
580 ret $31,($26),1 # L0 :
597 ret $31,($26),1 # L0 :
|
| A D | ev6-divide.S | 208 ret $31,($23),1 # L0 : L U U L
246 bsr $23,ufunction # L0: L U L U
261 ret $31,($23),1 # L0 : L U U L
|
| A D | ev6-memchr.S | 96 ret # L0 : L U L U
120 ret # L0 : L U L U
190 ret # L0 :
|
| A D | ev6-stxncpy.S | 133 ret (t9) # L0 : Latency=3
140 br $a_eos # L0 : Latency=3
312 ret (t9) # L0 : Latency=3
333 br $u_final # L0 : Latency=3
393 ret (t9) # L0 : Latency=3
|
| A D | ev6-memcpy.S | 87 ldq $6, 0($17) # L0 : bytes 0..7
176 ret $31, ($26), 1 # L0 :
240 ret $31, ($26), 1 # L0 :
|
| A D | ev6-copy_user.S | 119 br $31, $dirtyentry # L0 .. .. .. : L U U L
224 ret $31,($26),1 # L0 .. .. .. : L U L U
|
| A D | ev67-strlen.S | 48 ret $31, ($26) # L0 :
|
| A D | ev67-strcat.S | 53 br __stxcpy # L0 :
|
| A D | ev6-stxcpy.S | 109 ret (t9) # L0 : Latency=3
135 br stxcpy_aligned # L0 : Latency=3
259 ret (t9) # L0 : Latency=3
|
| A D | ev67-strchr.S | 87 ret # L0 :
|
| A D | ev6-csum_ipv6_magic.S | 150 ret # L0 : L U L U
|
| A D | ev67-strrchr.S | 106 ret # L0 : Latency=3
|
| /linux/Documentation/virt/kvm/ |
| A D | running-nested-guests.rst | 21 | L0 (Host Hypervisor) |
29 - L0 – level-0; the bare metal host, running KVM
31 - L1 – level-1 guest; a VM running on L0; also called the "guest
126 metal host (L0). Parameters for Intel hosts::
163 1. On the host hypervisor (L0), enable the ``nested`` parameter on
234 - Kernel, libvirt, and QEMU version from L0
244 - ``cat /sys/cpuinfo`` from L0
248 - ``lscpu`` from L0
252 - Full ``dmesg`` output from L0
262 - Output of: ``x86info -a`` from L0
[all …]
|
| A D | nested-vmx.rst | 33 L0, the guest hypervisor, which we call L1, and its nested guest, which we
74 also have "vmcs01", the VMCS that L0 built for L1, and "vmcs02" is the VMCS
75 which L0 builds to actually run L2 - how this is done is explained in the
|
| /linux/drivers/cpufreq/ |
| A D | s5pv210-cpufreq.c | 110 L0, L1, L2, L3, L4, enumerator
125 {0, L0, 1000*1000},
145 [L0] = {
264 if ((index == L0) || (priv_index == L0)) in s5pv210_target()
383 if (index == L0) in s5pv210_target()
|
| /linux/arch/xtensa/lib/ |
| A D | memset.S | 47 .L0: # return here from .Ldstunaligned when dst is aligned label
113 bbci.l a5, 1, .L0 # if now aligned, return to main algorithm
120 j .L0 # dst is now aligned, return to main algorithm
|
| /linux/arch/sh/lib/ |
| A D | __clear_user.S | 36 .L0: dt r3 define
38 bf/s .L0
|
| /linux/arch/sparc/net/ |
| A D | bpf_jit_64.h | 20 #define L0 0x10 macro
|
| /linux/arch/arm/mach-omap2/ |
| A D | sram243x.S | 62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
|
| A D | sram242x.S | 62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
|
| /linux/Documentation/translations/zh_CN/arm64/ |
| A D | memory.txt | 91 | +-------------------------------> [47:39] L0 索引
|
| /linux/arch/csky/abiv1/ |
| A D | memcpy.S | 35 .L0: label
116 jbf .L0
|
| /linux/Documentation/translations/zh_TW/arm64/ |
| A D | memory.txt | 95 | +-------------------------------> [47:39] L0 索引
|
| /linux/arch/arm/boot/dts/ |
| A D | aspeed-bmc-inventec-transformers.dts | 282 /*L0-L7*/ "","","","","","","","",
|