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Searched refs:L1_CACHE_BYTES (Results 1 – 25 of 180) sorted by relevance

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/linux/arch/sh/mm/
A Dflush-sh4.c21 & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region()
22 cnt = (end - v) / L1_CACHE_BYTES; in sh4__flush_wback_region()
25 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
26 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
27 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
28 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
29 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
30 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
31 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
55 & ~(L1_CACHE_BYTES-1); in sh4__flush_purge_region()
[all …]
A Dcache-sh2a.c57 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
59 & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
70 for (v = begin; v < end; v += L1_CACHE_BYTES) { in sh2a__flush_wback_region()
78 for (v = begin; v < end; v += L1_CACHE_BYTES) in sh2a__flush_wback_region()
99 & ~(L1_CACHE_BYTES-1); in sh2a__flush_purge_region()
104 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh2a__flush_purge_region()
129 & ~(L1_CACHE_BYTES-1); in sh2a__flush_invalidate_region()
139 for (v = begin; v < end; v += L1_CACHE_BYTES) in sh2a__flush_invalidate_region()
157 start = data->addr1 & ~(L1_CACHE_BYTES-1); in sh2a_flush_icache_range()
158 end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1); in sh2a_flush_icache_range()
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A Dcache-sh2.c23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_wback_region()
25 & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
26 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh2__flush_wback_region()
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
45 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_purge_region()
46 & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
48 for (v = begin; v < end; v+=L1_CACHE_BYTES) in sh2__flush_purge_region()
75 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_invalidate_region()
77 & ~(L1_CACHE_BYTES-1); in sh2__flush_invalidate_region()
[all …]
A Dcache-sh3.c38 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh3__flush_wback_region()
39 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh3__flush_wback_region()
40 & ~(L1_CACHE_BYTES-1); in sh3__flush_wback_region()
42 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh3__flush_wback_region()
76 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh3__flush_purge_region()
77 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh3__flush_purge_region()
78 & ~(L1_CACHE_BYTES-1); in sh3__flush_purge_region()
80 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh3__flush_purge_region()
/linux/arch/csky/mm/
A Dcachev2.c26 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in icache_inv_range()
28 for (; i < end; i += L1_CACHE_BYTES) in icache_inv_range()
54 for (; i < param->end; i += L1_CACHE_BYTES) in local_icache_inv_range()
81 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in dcache_wb_range()
83 for (; i < end; i += L1_CACHE_BYTES) in dcache_wb_range()
97 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in dma_wbinv_range()
99 for (; i < end; i += L1_CACHE_BYTES) in dma_wbinv_range()
106 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in dma_inv_range()
108 for (; i < end; i += L1_CACHE_BYTES) in dma_inv_range()
115 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in dma_wb_range()
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/linux/arch/arm/lib/
A Dcopy_page.S14 #define COPY_COUNT (PAGE_SZ / (2 * L1_CACHE_BYTES) PLD( -1 ))
27 PLD( pld [r1, #L1_CACHE_BYTES] )
30 1: PLD( pld [r1, #2 * L1_CACHE_BYTES])
31 PLD( pld [r1, #3 * L1_CACHE_BYTES])
33 .rept (2 * L1_CACHE_BYTES / 16 - 1)
/linux/arch/hexagon/include/asm/
A Dcache.h13 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
15 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
17 #define __cacheline_aligned __aligned(L1_CACHE_BYTES)
18 #define ____cacheline_aligned __aligned(L1_CACHE_BYTES)
/linux/arch/arc/kernel/
A Dvmlinux.lds.S62 INIT_TEXT_SECTION(L1_CACHE_BYTES)
67 INIT_SETUP(L1_CACHE_BYTES)
78 PERCPU_SECTION(L1_CACHE_BYTES)
96 EXCEPTION_TABLE(L1_CACHE_BYTES)
106 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
/linux/arch/csky/kernel/
A Dvmlinux.lds.S30 PERCPU_SECTION(L1_CACHE_BYTES)
55 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
106 EXCEPTION_TABLE(L1_CACHE_BYTES)
107 BSS_SECTION(L1_CACHE_BYTES, PAGE_SIZE, L1_CACHE_BYTES)
/linux/arch/powerpc/include/asm/
A Dpage_32.h16 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
48 WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1)); in clear_page()
50 for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES) in clear_page()
A Dcache.h30 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
32 #define SMP_CACHE_BYTES L1_CACHE_BYTES
85 return L1_CACHE_BYTES; in l1_dcache_bytes()
95 return L1_CACHE_BYTES; in l1_icache_bytes()
/linux/arch/alpha/include/asm/
A Dcache.h11 # define L1_CACHE_BYTES 64 macro
17 # define L1_CACHE_BYTES 32 macro
21 #define SMP_CACHE_BYTES L1_CACHE_BYTES
/linux/arch/xtensa/include/asm/
A Dcache.h17 #define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE macro
18 #define SMP_CACHE_BYTES L1_CACHE_BYTES
32 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux/arch/powerpc/lib/
A Dcopy_32.S64 CACHELINE_BYTES = L1_CACHE_BYTES
66 CACHELINE_MASK = (L1_CACHE_BYTES-1)
214 #if L1_CACHE_BYTES >= 32
216 #if L1_CACHE_BYTES >= 64
219 #if L1_CACHE_BYTES >= 128
393 #if L1_CACHE_BYTES >= 32
395 #if L1_CACHE_BYTES >= 64
398 #if L1_CACHE_BYTES >= 128
451 #if L1_CACHE_BYTES >= 32
453 #if L1_CACHE_BYTES >= 64
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A Dchecksum_32.S123 CACHELINE_BYTES = L1_CACHE_BYTES
125 CACHELINE_MASK = (L1_CACHE_BYTES-1)
198 #if L1_CACHE_BYTES >= 32
200 #if L1_CACHE_BYTES >= 64
203 #if L1_CACHE_BYTES >= 128
258 #if L1_CACHE_BYTES >= 32
260 #if L1_CACHE_BYTES >= 64
263 #if L1_CACHE_BYTES >= 128
/linux/include/linux/
A Dcache.h9 #define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES)
13 #define SMP_CACHE_BYTES L1_CACHE_BYTES
85 #define cache_line_size() L1_CACHE_BYTES
/linux/arch/nios2/kernel/
A Dvmlinux.lds.S42 EXCEPTION_TABLE(L1_CACHE_BYTES)
48 PERCPU_SECTION(L1_CACHE_BYTES)
53 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
/linux/arch/parisc/include/asm/
A Dcache.h16 #define L1_CACHE_BYTES 16 macro
21 #define SMP_CACHE_BYTES L1_CACHE_BYTES
23 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux/drivers/misc/sgi-xp/
A Dxpnet.c121 #define XPNET_MAX_MTU (0x800000UL - L1_CACHE_BYTES)
170 skb = dev_alloc_skb(msg->size + L1_CACHE_BYTES); in xpnet_receive()
173 msg->size + L1_CACHE_BYTES); in xpnet_receive()
187 skb_reserve(skb, (L1_CACHE_BYTES - ((u64)skb->data & in xpnet_receive()
188 (L1_CACHE_BYTES - 1)) + in xpnet_receive()
209 dst = (void *)((u64)skb->data & ~(L1_CACHE_BYTES - 1)); in xpnet_receive()
445 start_addr = ((u64)skb->data & ~(L1_CACHE_BYTES - 1)); in xpnet_dev_hard_start_xmit()
/linux/arch/powerpc/kernel/
A Dmisc_32.S236 rlwinm r5, r3, 0, L1_CACHE_BYTES - 1
251 addi r11,r11,L1_CACHE_BYTES
255 li r11,L1_CACHE_BYTES+4
257 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
265 #if L1_CACHE_BYTES >= 32
267 #if L1_CACHE_BYTES >= 64
270 #if L1_CACHE_BYTES >= 128
/linux/arch/riscv/kernel/
A Dvmlinux-xip.lds.S51 RO_DATA(L1_CACHE_BYTES)
75 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
127 PERCPU_SECTION(L1_CACHE_BYTES)
/linux/arch/arc/mm/
A Dcache.c251 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); in __cache_line_loop_v3()
273 paddr += L1_CACHE_BYTES; in __cache_line_loop_v3()
277 vaddr += L1_CACHE_BYTES; in __cache_line_loop_v3()
310 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); in __cache_line_loop_v4()
330 paddr += L1_CACHE_BYTES; in __cache_line_loop_v4()
363 sz += L1_CACHE_BYTES - 1; in __cache_line_loop_v4()
1144 if (ic->line_len != L1_CACHE_BYTES) in arc_cache_init_master()
1146 ic->line_len, L1_CACHE_BYTES); in arc_cache_init_master()
1164 if (dc->line_len != L1_CACHE_BYTES) in arc_cache_init_master()
1166 dc->line_len, L1_CACHE_BYTES); in arc_cache_init_master()
[all …]
/linux/arch/powerpc/kernel/vdso32/
A Dcacheflush.S42 li r5, L1_CACHE_BYTES - 1
61 addi r6, r6, L1_CACHE_BYTES
85 addi r7, r7, L1_CACHE_BYTES
/linux/arch/nds32/include/asm/
A Dcache.h7 #define L1_CACHE_BYTES 32 macro
10 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux/arch/m68k/include/asm/
A Dcache.h10 #define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT) macro
12 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES

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