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Searched refs:L3 (Results 1 – 25 of 79) sorted by relevance

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/linux/net/l3mdev/
A DKconfig3 # Configuration for L3 master device support
7 bool "L3 Master device support"
11 drivers to support L3 master devices like VRF.
/linux/Documentation/devicetree/bindings/interconnect/
A Dqcom,osm-l3.yaml7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
/linux/Documentation/networking/
A Dipvlan.rst13 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
42 L3 bridge mode::
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
64 that in L3 mode the slaves wont receive any multicast / broadcast traffic.
65 L3 mode is more restrictive since routing is controlled from the other (mostly)
76 4.2 L3 mode:
79 In this mode TX processing up to L3 happens on the stack instance attached
88 This is very similar to the L3 mode except that iptables (conn-tracking)
89 works in this mode and hence it is L3-symmetric (L3s). This will have slightly less
90 performance but that shouldn't matter since you are choosing this mode over plain-L3
A Dbareudp.rst7 There are various L3 encapsulation standards using UDP being discussed to
11 The Bareudp tunnel module provides a generic L3 encapsulation support for
12 tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel.
30 This creates a bareudp tunnel device which tunnels L3 traffic with ethertype
/linux/drivers/perf/
A DKconfig78 Unit (DSU). The DSU integrates one or more cores with an L3 memory
101 bool "Qualcomm Technologies L3-cache PMU"
105 Provides support for the L3 cache performance monitor unit (PMU)
107 Adds the L3 cache PMU into the perf events subsystem for
108 monitoring L3 cache events.
117 The SoC has PMU support in its L3 cache controller (L3C) and
/linux/Documentation/devicetree/bindings/edac/
A Dapm-xgene-edac.txt8 L3 - L3 cache controller
24 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
39 Required properties for L3 subnode:
42 - reg : First resource shall be the L3 EDAC resource.
/linux/Documentation/x86/
A Dresctrl.rst43 L2 and L3 CDP are controlled separately.
178 # echo L3:0=f7 > schemata
426 With CDP disabled the L3 schemata format is::
428 L3:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
454 Memory b/w domain is L3 cache.
462 Memory bandwidth domain is L3 cache.
711 of L3 cache on socket 0.
728 # echo "L3:0=f8000;1=fffff" > p0/schemata
742 # echo "L3:0=7c00;1=fffff" > p1/schemata
777 # echo "L3:0=3ff\nMB:0=50" > schemata
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/linux/arch/powerpc/perf/
A Disa207-common.c229 ret = PH(LVL, L3); in isa207_find_source()
249 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
251 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in isa207_find_source()
258 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
260 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
/linux/Documentation/admin-guide/perf/
A Dqcom_l3_pmu.rst2 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
A Darm_dsu_pmu.rst5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
7 allows counting the various events related to the L3 cache, Snoop Control Unit
/linux/Documentation/devicetree/bindings/sound/
A Domap-dmic.txt7 <L3 interconnect address, size>;
16 <0x4902e000 0x7f>; /* L3 Interconnect */
A Domap-mcpdm.txt7 <L3 interconnect address, size>;
18 <0x49032000 0x7f>; /* L3 Interconnect */
/linux/arch/x86/events/intel/
A Dds.c71 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
75 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
76 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
77 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
78 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
79 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
80 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
82 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
92 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
93 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
[all …]
/linux/arch/alpha/kernel/
A Dsetup.c1280 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1291 L3 = -1; in determine_cpu_caches()
1312 L3 = -1; in determine_cpu_caches()
1343 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1357 L3 = -1; in determine_cpu_caches()
1380 L3 = -1; in determine_cpu_caches()
1387 L3 = -1; in determine_cpu_caches()
1392 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1399 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/linux/Documentation/devicetree/bindings/arm/omap/
A Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
/linux/arch/m68k/lib/
A Ddivsi3.S117 jpl L3
120 L3: movel sp@+, d2 label
A Dudivsi3.S95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
/linux/Documentation/translations/zh_CN/arm64/
A Dmemory.txt88 | | | | +-> [20:12] L3 索引
103 | | | +----------> [28:16] L3 索引
/linux/arch/riscv/lib/
A Dtishift.S33 beqz a2, .L3
44 .L3: label
/linux/Documentation/translations/zh_TW/arm64/
A Dmemory.txt92 | | | | +-> [20:12] L3 索引
107 | | | +----------> [28:16] L3 索引
/linux/arch/arm/boot/dts/
A Domap4-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
143 <0x49024000 0xff>; /* L3 Interconnect */
176 <0x49026000 0xff>; /* L3 Interconnect */
210 <0x4902a000 0x1000>; /* L3 data port */
246 <0x4902e000 0x7f>; /* L3 Interconnect */
308 <0x49032000 0x7f>; /* L3 Interconnect */
A Domap5-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
143 <0x49024000 0xff>; /* L3 Interconnect */
176 <0x49026000 0xff>; /* L3 Interconnect */
228 <0x4902e000 0x7f>; /* L3 Interconnect */
271 <0x49032000 0x7f>; /* L3 Interconnect */
A Dgemini-wbd111.dts45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
/linux/drivers/cpufreq/
A Ds5pv210-cpufreq.c110 L0, L1, L2, L3, L4, enumerator
128 {0, L3, 200*1000},
157 [L3] = {
367 if (index >= L3) in s5pv210_target()
/linux/Documentation/locking/
A Drt-mutex-design.rst139 Mutexes: L1, L2, L3, L4
145 C owns L3
152 E->L4->D->L3->C->L2->B->L1->A
166 E->L4->D->L3->C->L2-+
185 E->L4->D->L3->C-+
257 mutex_lock(L3);
261 mutex_unlock(L3);
267 mutex_lock(L3);
271 mutex_unlock(L3);
279 D owns L3
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