| /linux/drivers/video/fbdev/matrox/ |
| A D | matroxfb_maven.c | 548 LR(0x00); LR(0x01); LR(0x02); LR(0x03); in maven_init_TV()
550 LR(0x04); in maven_init_TV()
552 LR(0x2C); in maven_init_TV()
553 LR(0x08); in maven_init_TV()
554 LR(0x0A); in maven_init_TV()
555 LR(0x09); in maven_init_TV()
556 LR(0x29); in maven_init_TV()
559 LR(0x0B); in maven_init_TV()
560 LR(0x0C); in maven_init_TV()
575 LR(0x34); in maven_init_TV()
[all …]
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| A D | matroxfb_g450.c | 503 #define LR(x) cve2_set_reg(minfo, (x), m->regs[(x)]) macro
509 LR(0x80); in cve2_init_TV()
510 LR(0x82); LR(0x83); in cve2_init_TV()
511 LR(0x84); LR(0x85); in cve2_init_TV()
516 LR(i); in cve2_init_TV()
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| /linux/arch/arm/kernel/ |
| A D | entry-ftrace.S | 74 @ OLD_R0 will overwrite previous LR
79 str lr, [sp, #0] @ store LR instead of PC
81 ldr lr, [sp, #8] @ get previous LR
83 str r0, [sp, #8] @ write r0 as OLD_R0 over previous LR
90 @ R0 | R1 | ... | LR | SP + 4 | previous LR | LR | PSR | OLD_R0 |
100 ldr lr, [sp, #S_PC] @ get LR
117 ldr lr, [sp, #4] @ restore LR
137 ldr lr, [sp, #4] @ restore LR
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| A D | unwind.c | 72 LR = 14, enumerator
341 ctrl->vrs[PC] = ctrl->vrs[LR]; in unwind_exec_insn()
366 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); in unwind_exec_insn()
400 ctrl.vrs[LR] = frame->lr; in unwind_frame()
445 ctrl.vrs[PC] = ctrl.vrs[LR]; in unwind_frame()
453 frame->lr = ctrl.vrs[LR]; in unwind_frame()
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| A D | entry-header.S | 174 @ Store/load the USER SP and LR registers by switching to the SYS
|
| /linux/tools/perf/arch/arm/tests/ |
| A D | regs_load.S | 18 #define LR 0x70 macro
55 str lr, [r0, #LR]
|
| /linux/arch/powerpc/kernel/ |
| A D | swsusp_asm64.S | 89 SAVE_SPECIAL(LR)
135 RESTORE_SPECIAL(LR)
269 RESTORE_SPECIAL(LR)
|
| /linux/tools/perf/arch/csky/util/ |
| A D | unwind-libdw.c | 37 dwarf_regs[15] = REG(LR); in libdw__arch_set_initial_registers()
71 dwarf_regs[15] = REG(LR); in libdw__arch_set_initial_registers()
|
| /linux/Documentation/devicetree/bindings/display/panel/ |
| A D | sharp,ls037v7dw01.yaml | 35 GPIO ordered MO, LR, and UD as specified in LS037V7DW01.pdf
58 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
|
| /linux/Documentation/gpu/ |
| A D | komeda-kms.rst | 102 rankdir=LR;
148 rankdir=LR;
226 rankdir=LR;
242 rankdir=LR;
257 rankdir=LR;
273 rankdir=LR;
289 rankdir=LR;
|
| /linux/arch/arm/lib/ |
| A D | backtrace.S | 67 bic sv_pc, sv_pc, mask @ mask PC/LR for the mode
77 bic r1, r1, mask @ mask PC/LR for the mode
|
| /linux/arch/arm/mm/ |
| A D | proc-v7m.S | 133 mov r6, lr @ save LR
142 mov lr, r6 @ restore LR
|
| /linux/tools/perf/arch/arm/util/ |
| A D | unwind-libdw.c | 33 dwarf_regs[14] = REG(LR); in libdw__arch_set_initial_registers()
|
| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| A D | ixgbe.rst | 59 | LR Modules |
61 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | FTLX1471D3BCV-IT |
63 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | AFCT-701SDZ-IN2 |
65 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | AFCT-701SDDZ-IN1 |
78 | Finisar | SFP+ LR bailed, 10g single rate | FTLX1471D3BCL |
84 | Finisar | DUAL RATE 1G/10G SFP+ LR (No Bail) | FTLX1471D3QCV-IT |
86 | Avago | DUAL RATE 1G/10G SFP+ LR (No Bail) | AFCT-701SDZ-IN1 |
139 - LAN on Motherboard (LOMs) may support DA, SR, or LR modules. Other module
152 | Finisar | SFP+ LR bailed, 10g single rate | FTLX1471D3BCL |
|
| A D | ixgb.rst | 59 | 82597EX | Intel(R) PRO/10GbE LR/SR/CX4 | - 10G Base-LR (fiber) |
|
| /linux/net/ieee802154/ |
| A D | Kconfig | 11 Say Y here to compile LR-WPAN support into the kernel or say M to
|
| /linux/tools/perf/arch/arm64/util/ |
| A D | unwind-libdw.c | 49 dwarf_regs[30] = REG(LR); in libdw__arch_set_initial_registers()
|
| /linux/Documentation/livepatch/ |
| A D | reliable-stacktrace.rst | 289 Similarly, a function may deliberately clobber the LR, e.g.
296 ADR LR, <callee>
297 BLR LR
301 The ADR places the address of 'callee' into the LR, before the BLR branches to
308 reliably identify when the LR or stack value should be used (e.g. using
|
| /linux/arch/powerpc/platforms/52xx/ |
| A D | lite5200_sleep.S | 69 SAVE_SPRN(LR, 0x1c)
247 LOAD_SPRN(LR, 0x1c)
|
| /linux/tools/testing/selftests/powerpc/switch_endian/ |
| A D | check.S | 26 addi r9,r15,32 # check LR
|
| /linux/Documentation/devicetree/bindings/phy/ |
| A D | microchip,sparx5-serdes.yaml | 63 * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
|
| /linux/arch/arm/boot/dts/ |
| A D | omap3-evm-common.dtsi | 105 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
|
| /linux/net/ethtool/ |
| A D | common.c | 155 __DEFINE_LINK_MODE_NAME(10000, LR, Full),
303 __DEFINE_LINK_MODE_PARAMS(10000, LR, Full),
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| /linux/arch/powerpc/platforms/8xx/ |
| A D | Kconfig | 120 (by not placing conditional branches or branches to LR or CTR
|
| /linux/Documentation/powerpc/ |
| A D | syscall64-abi.rst | 45 stack frame LR and CR save fields are not used.
|