1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Atmel MACB Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7 #ifndef _MACB_H
8 #define _MACB_H
9
10 #include <linux/clk.h>
11 #include <linux/phylink.h>
12 #include <linux/ptp_clock_kernel.h>
13 #include <linux/net_tstamp.h>
14 #include <linux/interrupt.h>
15
16 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
17 #define MACB_EXT_DESC
18 #endif
19
20 #define MACB_GREGS_NBR 16
21 #define MACB_GREGS_VERSION 2
22 #define MACB_MAX_QUEUES 8
23
24 /* MACB register offsets */
25 #define MACB_NCR 0x0000 /* Network Control */
26 #define MACB_NCFGR 0x0004 /* Network Config */
27 #define MACB_NSR 0x0008 /* Network Status */
28 #define MACB_TAR 0x000c /* AT91RM9200 only */
29 #define MACB_TCR 0x0010 /* AT91RM9200 only */
30 #define MACB_TSR 0x0014 /* Transmit Status */
31 #define MACB_RBQP 0x0018 /* RX Q Base Address */
32 #define MACB_TBQP 0x001c /* TX Q Base Address */
33 #define MACB_RSR 0x0020 /* Receive Status */
34 #define MACB_ISR 0x0024 /* Interrupt Status */
35 #define MACB_IER 0x0028 /* Interrupt Enable */
36 #define MACB_IDR 0x002c /* Interrupt Disable */
37 #define MACB_IMR 0x0030 /* Interrupt Mask */
38 #define MACB_MAN 0x0034 /* PHY Maintenance */
39 #define MACB_PTR 0x0038
40 #define MACB_PFR 0x003c
41 #define MACB_FTO 0x0040
42 #define MACB_SCF 0x0044
43 #define MACB_MCF 0x0048
44 #define MACB_FRO 0x004c
45 #define MACB_FCSE 0x0050
46 #define MACB_ALE 0x0054
47 #define MACB_DTF 0x0058
48 #define MACB_LCOL 0x005c
49 #define MACB_EXCOL 0x0060
50 #define MACB_TUND 0x0064
51 #define MACB_CSE 0x0068
52 #define MACB_RRE 0x006c
53 #define MACB_ROVR 0x0070
54 #define MACB_RSE 0x0074
55 #define MACB_ELE 0x0078
56 #define MACB_RJA 0x007c
57 #define MACB_USF 0x0080
58 #define MACB_STE 0x0084
59 #define MACB_RLE 0x0088
60 #define MACB_TPF 0x008c
61 #define MACB_HRB 0x0090
62 #define MACB_HRT 0x0094
63 #define MACB_SA1B 0x0098
64 #define MACB_SA1T 0x009c
65 #define MACB_SA2B 0x00a0
66 #define MACB_SA2T 0x00a4
67 #define MACB_SA3B 0x00a8
68 #define MACB_SA3T 0x00ac
69 #define MACB_SA4B 0x00b0
70 #define MACB_SA4T 0x00b4
71 #define MACB_TID 0x00b8
72 #define MACB_TPQ 0x00bc
73 #define MACB_USRIO 0x00c0
74 #define MACB_WOL 0x00c4
75 #define MACB_MID 0x00fc
76 #define MACB_TBQPH 0x04C8
77 #define MACB_RBQPH 0x04D4
78
79 /* GEM register offsets. */
80 #define GEM_NCR 0x0000 /* Network Control */
81 #define GEM_NCFGR 0x0004 /* Network Config */
82 #define GEM_USRIO 0x000c /* User IO */
83 #define GEM_DMACFG 0x0010 /* DMA Configuration */
84 #define GEM_JML 0x0048 /* Jumbo Max Length */
85 #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
86 #define GEM_HRB 0x0080 /* Hash Bottom */
87 #define GEM_HRT 0x0084 /* Hash Top */
88 #define GEM_SA1B 0x0088 /* Specific1 Bottom */
89 #define GEM_SA1T 0x008C /* Specific1 Top */
90 #define GEM_SA2B 0x0090 /* Specific2 Bottom */
91 #define GEM_SA2T 0x0094 /* Specific2 Top */
92 #define GEM_SA3B 0x0098 /* Specific3 Bottom */
93 #define GEM_SA3T 0x009C /* Specific3 Top */
94 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
95 #define GEM_SA4T 0x00A4 /* Specific4 Top */
96 #define GEM_WOL 0x00b8 /* Wake on LAN */
97 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
98 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
99 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
100 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
101 #define GEM_OTX 0x0100 /* Octets transmitted */
102 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
103 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
104 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
105 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
106 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
107 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
108 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
109 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
110 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
111 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
112 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
113 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
114 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
115 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
116 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
117 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
118 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
119 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
120 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
121 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
122 #define GEM_ORX 0x0150 /* Octets received */
123 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
124 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
125 #define GEM_RXCNT 0x0158 /* Frames Received Counter */
126 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
127 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
128 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
129 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
130 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
131 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
132 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
133 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
134 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
135 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
136 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
137 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
138 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
139 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
140 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
141 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
142 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
143 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
144 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
145 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
146 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
147 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
148 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
149 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
150 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
151 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
152 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */
153 #define GEM_TI 0x01dc /* 1588 Timer Increment */
154 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
155 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
156 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
157 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
158 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
159 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
160 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
161 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
162 #define GEM_PCSCNTRL 0x0200 /* PCS Control */
163 #define GEM_PCSSTS 0x0204 /* PCS Status */
164 #define GEM_PCSPHYTOPID 0x0208 /* PCS PHY Top ID */
165 #define GEM_PCSPHYBOTID 0x020c /* PCS PHY Bottom ID */
166 #define GEM_PCSANADV 0x0210 /* PCS AN Advertisement */
167 #define GEM_PCSANLPBASE 0x0214 /* PCS AN Link Partner Base */
168 #define GEM_PCSANEXP 0x0218 /* PCS AN Expansion */
169 #define GEM_PCSANNPTX 0x021c /* PCS AN Next Page TX */
170 #define GEM_PCSANNPLP 0x0220 /* PCS AN Next Page LP */
171 #define GEM_PCSANEXTSTS 0x023c /* PCS AN Extended Status */
172 #define GEM_DCFG1 0x0280 /* Design Config 1 */
173 #define GEM_DCFG2 0x0284 /* Design Config 2 */
174 #define GEM_DCFG3 0x0288 /* Design Config 3 */
175 #define GEM_DCFG4 0x028c /* Design Config 4 */
176 #define GEM_DCFG5 0x0290 /* Design Config 5 */
177 #define GEM_DCFG6 0x0294 /* Design Config 6 */
178 #define GEM_DCFG7 0x0298 /* Design Config 7 */
179 #define GEM_DCFG8 0x029C /* Design Config 8 */
180 #define GEM_DCFG10 0x02A4 /* Design Config 10 */
181 #define GEM_DCFG12 0x02AC /* Design Config 12 */
182 #define GEM_USX_CONTROL 0x0A80 /* High speed PCS control register */
183 #define GEM_USX_STATUS 0x0A88 /* High speed PCS status register */
184
185 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
186 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
187
188 /* Screener Type 2 match registers */
189 #define GEM_SCRT2 0x540
190
191 /* EtherType registers */
192 #define GEM_ETHT 0x06E0
193
194 /* Type 2 compare registers */
195 #define GEM_T2CMPW0 0x0700
196 #define GEM_T2CMPW1 0x0704
197 #define T2CMP_OFST(t2idx) (t2idx * 2)
198
199 /* type 2 compare registers
200 * each location requires 3 compare regs
201 */
202 #define GEM_IP4SRC_CMP(idx) (idx * 3)
203 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
204 #define GEM_PORT_CMP(idx) (idx * 3 + 2)
205
206 /* Which screening type 2 EtherType register will be used (0 - 7) */
207 #define SCRT2_ETHT 0
208
209 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
210 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
211 #define GEM_TBQPH(hw_q) (0x04C8)
212 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
213 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
214 #define GEM_RBQPH(hw_q) (0x04D4)
215 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
216 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
217 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
218
219 /* Bitfields in NCR */
220 #define MACB_LB_OFFSET 0 /* reserved */
221 #define MACB_LB_SIZE 1
222 #define MACB_LLB_OFFSET 1 /* Loop back local */
223 #define MACB_LLB_SIZE 1
224 #define MACB_RE_OFFSET 2 /* Receive enable */
225 #define MACB_RE_SIZE 1
226 #define MACB_TE_OFFSET 3 /* Transmit enable */
227 #define MACB_TE_SIZE 1
228 #define MACB_MPE_OFFSET 4 /* Management port enable */
229 #define MACB_MPE_SIZE 1
230 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
231 #define MACB_CLRSTAT_SIZE 1
232 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
233 #define MACB_INCSTAT_SIZE 1
234 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
235 #define MACB_WESTAT_SIZE 1
236 #define MACB_BP_OFFSET 8 /* Back pressure */
237 #define MACB_BP_SIZE 1
238 #define MACB_TSTART_OFFSET 9 /* Start transmission */
239 #define MACB_TSTART_SIZE 1
240 #define MACB_THALT_OFFSET 10 /* Transmit halt */
241 #define MACB_THALT_SIZE 1
242 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
243 #define MACB_NCR_TPF_SIZE 1
244 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
245 #define MACB_TZQ_SIZE 1
246 #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */
247 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
248 #define MACB_OSSMODE_SIZE 1
249 #define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */
250 #define MACB_MIIONRGMII_SIZE 1
251
252 /* Bitfields in NCFGR */
253 #define MACB_SPD_OFFSET 0 /* Speed */
254 #define MACB_SPD_SIZE 1
255 #define MACB_FD_OFFSET 1 /* Full duplex */
256 #define MACB_FD_SIZE 1
257 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
258 #define MACB_BIT_RATE_SIZE 1
259 #define MACB_JFRAME_OFFSET 3 /* reserved */
260 #define MACB_JFRAME_SIZE 1
261 #define MACB_CAF_OFFSET 4 /* Copy all frames */
262 #define MACB_CAF_SIZE 1
263 #define MACB_NBC_OFFSET 5 /* No broadcast */
264 #define MACB_NBC_SIZE 1
265 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
266 #define MACB_NCFGR_MTI_SIZE 1
267 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
268 #define MACB_UNI_SIZE 1
269 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
270 #define MACB_BIG_SIZE 1
271 #define MACB_EAE_OFFSET 9 /* External address match enable */
272 #define MACB_EAE_SIZE 1
273 #define MACB_CLK_OFFSET 10
274 #define MACB_CLK_SIZE 2
275 #define MACB_RTY_OFFSET 12 /* Retry test */
276 #define MACB_RTY_SIZE 1
277 #define MACB_PAE_OFFSET 13 /* Pause enable */
278 #define MACB_PAE_SIZE 1
279 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
280 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
281 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
282 #define MACB_RBOF_SIZE 2
283 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
284 #define MACB_RLCE_SIZE 1
285 #define MACB_DRFCS_OFFSET 17 /* FCS remove */
286 #define MACB_DRFCS_SIZE 1
287 #define MACB_EFRHD_OFFSET 18
288 #define MACB_EFRHD_SIZE 1
289 #define MACB_IRXFCS_OFFSET 19
290 #define MACB_IRXFCS_SIZE 1
291
292 /* GEM specific NCR bitfields. */
293 #define GEM_ENABLE_HS_MAC_OFFSET 31
294 #define GEM_ENABLE_HS_MAC_SIZE 1
295
296 /* GEM specific NCFGR bitfields. */
297 #define GEM_FD_OFFSET 1 /* Full duplex */
298 #define GEM_FD_SIZE 1
299 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
300 #define GEM_GBE_SIZE 1
301 #define GEM_PCSSEL_OFFSET 11
302 #define GEM_PCSSEL_SIZE 1
303 #define GEM_PAE_OFFSET 13 /* Pause enable */
304 #define GEM_PAE_SIZE 1
305 #define GEM_CLK_OFFSET 18 /* MDC clock division */
306 #define GEM_CLK_SIZE 3
307 #define GEM_DBW_OFFSET 21 /* Data bus width */
308 #define GEM_DBW_SIZE 2
309 #define GEM_RXCOEN_OFFSET 24
310 #define GEM_RXCOEN_SIZE 1
311 #define GEM_SGMIIEN_OFFSET 27
312 #define GEM_SGMIIEN_SIZE 1
313
314
315 /* Constants for data bus width. */
316 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
317 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
318 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
319
320 /* Bitfields in DMACFG. */
321 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
322 #define GEM_FBLDO_SIZE 5
323 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
324 #define GEM_ENDIA_DESC_SIZE 1
325 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
326 #define GEM_ENDIA_PKT_SIZE 1
327 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
328 #define GEM_RXBMS_SIZE 2
329 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
330 #define GEM_TXPBMS_SIZE 1
331 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
332 #define GEM_TXCOEN_SIZE 1
333 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
334 #define GEM_RXBS_SIZE 8
335 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
336 #define GEM_DDRP_SIZE 1
337 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
338 #define GEM_RXEXT_SIZE 1
339 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
340 #define GEM_TXEXT_SIZE 1
341 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
342 #define GEM_ADDR64_SIZE 1
343
344
345 /* Bitfields in NSR */
346 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
347 #define MACB_NSR_LINK_SIZE 1
348 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
349 #define MACB_MDIO_SIZE 1
350 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
351 #define MACB_IDLE_SIZE 1
352
353 /* Bitfields in TSR */
354 #define MACB_UBR_OFFSET 0 /* Used bit read */
355 #define MACB_UBR_SIZE 1
356 #define MACB_COL_OFFSET 1 /* Collision occurred */
357 #define MACB_COL_SIZE 1
358 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
359 #define MACB_TSR_RLE_SIZE 1
360 #define MACB_TGO_OFFSET 3 /* Transmit go */
361 #define MACB_TGO_SIZE 1
362 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
363 #define MACB_BEX_SIZE 1
364 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
365 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
366 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
367 #define MACB_COMP_SIZE 1
368 #define MACB_UND_OFFSET 6 /* Trnasmit under run */
369 #define MACB_UND_SIZE 1
370
371 /* Bitfields in RSR */
372 #define MACB_BNA_OFFSET 0 /* Buffer not available */
373 #define MACB_BNA_SIZE 1
374 #define MACB_REC_OFFSET 1 /* Frame received */
375 #define MACB_REC_SIZE 1
376 #define MACB_OVR_OFFSET 2 /* Receive overrun */
377 #define MACB_OVR_SIZE 1
378
379 /* Bitfields in ISR/IER/IDR/IMR */
380 #define MACB_MFD_OFFSET 0 /* Management frame sent */
381 #define MACB_MFD_SIZE 1
382 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
383 #define MACB_RCOMP_SIZE 1
384 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
385 #define MACB_RXUBR_SIZE 1
386 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
387 #define MACB_TXUBR_SIZE 1
388 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
389 #define MACB_ISR_TUND_SIZE 1
390 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
391 #define MACB_ISR_RLE_SIZE 1
392 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
393 #define MACB_TXERR_SIZE 1
394 #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */
395 #define MACB_RM9200_TBRE_SIZE 1
396 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
397 #define MACB_TCOMP_SIZE 1
398 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
399 #define MACB_ISR_LINK_SIZE 1
400 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
401 #define MACB_ISR_ROVR_SIZE 1
402 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
403 #define MACB_HRESP_SIZE 1
404 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
405 #define MACB_PFR_SIZE 1
406 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
407 #define MACB_PTZ_SIZE 1
408 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
409 #define MACB_WOL_SIZE 1
410 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
411 #define MACB_DRQFR_SIZE 1
412 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
413 #define MACB_SFR_SIZE 1
414 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
415 #define MACB_DRQFT_SIZE 1
416 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
417 #define MACB_SFT_SIZE 1
418 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
419 #define MACB_PDRQFR_SIZE 1
420 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
421 #define MACB_PDRSFR_SIZE 1
422 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
423 #define MACB_PDRQFT_SIZE 1
424 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
425 #define MACB_PDRSFT_SIZE 1
426 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
427 #define MACB_SRI_SIZE 1
428 #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
429 #define GEM_WOL_SIZE 1
430
431 /* Timer increment fields */
432 #define MACB_TI_CNS_OFFSET 0
433 #define MACB_TI_CNS_SIZE 8
434 #define MACB_TI_ACNS_OFFSET 8
435 #define MACB_TI_ACNS_SIZE 8
436 #define MACB_TI_NIT_OFFSET 16
437 #define MACB_TI_NIT_SIZE 8
438
439 /* Bitfields in MAN */
440 #define MACB_DATA_OFFSET 0 /* data */
441 #define MACB_DATA_SIZE 16
442 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
443 #define MACB_CODE_SIZE 2
444 #define MACB_REGA_OFFSET 18 /* Register address */
445 #define MACB_REGA_SIZE 5
446 #define MACB_PHYA_OFFSET 23 /* PHY address */
447 #define MACB_PHYA_SIZE 5
448 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
449 #define MACB_RW_SIZE 2
450 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
451 #define MACB_SOF_SIZE 2
452
453 /* Bitfields in USRIO (AVR32) */
454 #define MACB_MII_OFFSET 0
455 #define MACB_MII_SIZE 1
456 #define MACB_EAM_OFFSET 1
457 #define MACB_EAM_SIZE 1
458 #define MACB_TX_PAUSE_OFFSET 2
459 #define MACB_TX_PAUSE_SIZE 1
460 #define MACB_TX_PAUSE_ZERO_OFFSET 3
461 #define MACB_TX_PAUSE_ZERO_SIZE 1
462
463 /* Bitfields in USRIO (AT91) */
464 #define MACB_RMII_OFFSET 0
465 #define MACB_RMII_SIZE 1
466 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
467 #define GEM_RGMII_SIZE 1
468 #define MACB_CLKEN_OFFSET 1
469 #define MACB_CLKEN_SIZE 1
470
471 /* Bitfields in WOL */
472 #define MACB_IP_OFFSET 0
473 #define MACB_IP_SIZE 16
474 #define MACB_MAG_OFFSET 16
475 #define MACB_MAG_SIZE 1
476 #define MACB_ARP_OFFSET 17
477 #define MACB_ARP_SIZE 1
478 #define MACB_SA1_OFFSET 18
479 #define MACB_SA1_SIZE 1
480 #define MACB_WOL_MTI_OFFSET 19
481 #define MACB_WOL_MTI_SIZE 1
482
483 /* Bitfields in MID */
484 #define MACB_IDNUM_OFFSET 16
485 #define MACB_IDNUM_SIZE 12
486 #define MACB_REV_OFFSET 0
487 #define MACB_REV_SIZE 16
488
489 /* Bitfield in HS_MAC_CONFIG */
490 #define GEM_HS_MAC_SPEED_OFFSET 0
491 #define GEM_HS_MAC_SPEED_SIZE 3
492
493 /* Bitfields in PCSCNTRL */
494 #define GEM_PCSAUTONEG_OFFSET 12
495 #define GEM_PCSAUTONEG_SIZE 1
496
497 /* Bitfields in DCFG1. */
498 #define GEM_IRQCOR_OFFSET 23
499 #define GEM_IRQCOR_SIZE 1
500 #define GEM_DBWDEF_OFFSET 25
501 #define GEM_DBWDEF_SIZE 3
502 #define GEM_NO_PCS_OFFSET 0
503 #define GEM_NO_PCS_SIZE 1
504
505 /* Bitfields in DCFG2. */
506 #define GEM_RX_PKT_BUFF_OFFSET 20
507 #define GEM_RX_PKT_BUFF_SIZE 1
508 #define GEM_TX_PKT_BUFF_OFFSET 21
509 #define GEM_TX_PKT_BUFF_SIZE 1
510
511
512 /* Bitfields in DCFG5. */
513 #define GEM_TSU_OFFSET 8
514 #define GEM_TSU_SIZE 1
515
516 /* Bitfields in DCFG6. */
517 #define GEM_PBUF_LSO_OFFSET 27
518 #define GEM_PBUF_LSO_SIZE 1
519 #define GEM_DAW64_OFFSET 23
520 #define GEM_DAW64_SIZE 1
521
522 /* Bitfields in DCFG8. */
523 #define GEM_T1SCR_OFFSET 24
524 #define GEM_T1SCR_SIZE 8
525 #define GEM_T2SCR_OFFSET 16
526 #define GEM_T2SCR_SIZE 8
527 #define GEM_SCR2ETH_OFFSET 8
528 #define GEM_SCR2ETH_SIZE 8
529 #define GEM_SCR2CMP_OFFSET 0
530 #define GEM_SCR2CMP_SIZE 8
531
532 /* Bitfields in DCFG10 */
533 #define GEM_TXBD_RDBUFF_OFFSET 12
534 #define GEM_TXBD_RDBUFF_SIZE 4
535 #define GEM_RXBD_RDBUFF_OFFSET 8
536 #define GEM_RXBD_RDBUFF_SIZE 4
537
538 /* Bitfields in DCFG12. */
539 #define GEM_HIGH_SPEED_OFFSET 26
540 #define GEM_HIGH_SPEED_SIZE 1
541
542 /* Bitfields in USX_CONTROL. */
543 #define GEM_USX_CTRL_SPEED_OFFSET 14
544 #define GEM_USX_CTRL_SPEED_SIZE 3
545 #define GEM_SERDES_RATE_OFFSET 12
546 #define GEM_SERDES_RATE_SIZE 2
547 #define GEM_RX_SCR_BYPASS_OFFSET 9
548 #define GEM_RX_SCR_BYPASS_SIZE 1
549 #define GEM_TX_SCR_BYPASS_OFFSET 8
550 #define GEM_TX_SCR_BYPASS_SIZE 1
551 #define GEM_TX_EN_OFFSET 1
552 #define GEM_TX_EN_SIZE 1
553 #define GEM_SIGNAL_OK_OFFSET 0
554 #define GEM_SIGNAL_OK_SIZE 1
555
556 /* Bitfields in USX_STATUS. */
557 #define GEM_USX_BLOCK_LOCK_OFFSET 0
558 #define GEM_USX_BLOCK_LOCK_SIZE 1
559
560 /* Bitfields in TISUBN */
561 #define GEM_SUBNSINCR_OFFSET 0
562 #define GEM_SUBNSINCRL_OFFSET 24
563 #define GEM_SUBNSINCRL_SIZE 8
564 #define GEM_SUBNSINCRH_OFFSET 0
565 #define GEM_SUBNSINCRH_SIZE 16
566 #define GEM_SUBNSINCR_SIZE 24
567
568 /* Bitfields in TI */
569 #define GEM_NSINCR_OFFSET 0
570 #define GEM_NSINCR_SIZE 8
571
572 /* Bitfields in TSH */
573 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
574 #define GEM_TSH_SIZE 16
575
576 /* Bitfields in TSL */
577 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
578 #define GEM_TSL_SIZE 32
579
580 /* Bitfields in TN */
581 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
582 #define GEM_TN_SIZE 30
583
584 /* Bitfields in TXBDCTRL */
585 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
586 #define GEM_TXTSMODE_SIZE 2
587
588 /* Bitfields in RXBDCTRL */
589 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
590 #define GEM_RXTSMODE_SIZE 2
591
592 /* Bitfields in SCRT2 */
593 #define GEM_QUEUE_OFFSET 0 /* Queue Number */
594 #define GEM_QUEUE_SIZE 4
595 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
596 #define GEM_VLANPR_SIZE 3
597 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
598 #define GEM_VLANEN_SIZE 1
599 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
600 #define GEM_ETHT2IDX_SIZE 3
601 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
602 #define GEM_ETHTEN_SIZE 1
603 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
604 #define GEM_CMPA_SIZE 5
605 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
606 #define GEM_CMPAEN_SIZE 1
607 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
608 #define GEM_CMPB_SIZE 5
609 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
610 #define GEM_CMPBEN_SIZE 1
611 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
612 #define GEM_CMPC_SIZE 5
613 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
614 #define GEM_CMPCEN_SIZE 1
615
616 /* Bitfields in ETHT */
617 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
618 #define GEM_ETHTCMP_SIZE 16
619
620 /* Bitfields in T2CMPW0 */
621 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
622 #define GEM_T2CMP_SIZE 16
623 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
624 #define GEM_T2MASK_SIZE 16
625
626 /* Bitfields in T2CMPW1 */
627 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */
628 #define GEM_T2DISMSK_SIZE 1
629 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
630 #define GEM_T2CMPOFST_SIZE 2
631 #define GEM_T2OFST_OFFSET 0 /* offset value */
632 #define GEM_T2OFST_SIZE 7
633
634 /* Offset for screener type 2 compare values (T2CMPOFST).
635 * Note the offset is applied after the specified point,
636 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
637 * of 12 bytes from this would be the source IP address in an IP header
638 */
639 #define GEM_T2COMPOFST_SOF 0
640 #define GEM_T2COMPOFST_ETYPE 1
641 #define GEM_T2COMPOFST_IPHDR 2
642 #define GEM_T2COMPOFST_TCPUDP 3
643
644 /* offset from EtherType to IP address */
645 #define ETYPE_SRCIP_OFFSET 12
646 #define ETYPE_DSTIP_OFFSET 16
647
648 /* offset from IP header to port */
649 #define IPHDR_SRCPORT_OFFSET 0
650 #define IPHDR_DSTPORT_OFFSET 2
651
652 /* Transmit DMA buffer descriptor Word 1 */
653 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
654 #define GEM_DMA_TXVALID_SIZE 1
655
656 /* Receive DMA buffer descriptor Word 0 */
657 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
658 #define GEM_DMA_RXVALID_SIZE 1
659
660 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
661 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
662 #define GEM_DMA_SECL_SIZE 2
663 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
664 #define GEM_DMA_NSEC_SIZE 30
665
666 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
667
668 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
669 * Old hardware supports only 6 bit precision but it is enough for PTP.
670 * Less accuracy is used always instead of checking hardware version.
671 */
672 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
673 #define GEM_DMA_SECH_SIZE 4
674 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
675 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
676 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
677
678 /* Bitfields in ADJ */
679 #define GEM_ADDSUB_OFFSET 31
680 #define GEM_ADDSUB_SIZE 1
681 /* Constants for CLK */
682 #define MACB_CLK_DIV8 0
683 #define MACB_CLK_DIV16 1
684 #define MACB_CLK_DIV32 2
685 #define MACB_CLK_DIV64 3
686
687 /* GEM specific constants for CLK. */
688 #define GEM_CLK_DIV8 0
689 #define GEM_CLK_DIV16 1
690 #define GEM_CLK_DIV32 2
691 #define GEM_CLK_DIV48 3
692 #define GEM_CLK_DIV64 4
693 #define GEM_CLK_DIV96 5
694
695 /* Constants for MAN register */
696 #define MACB_MAN_C22_SOF 1
697 #define MACB_MAN_C22_WRITE 1
698 #define MACB_MAN_C22_READ 2
699 #define MACB_MAN_C22_CODE 2
700
701 #define MACB_MAN_C45_SOF 0
702 #define MACB_MAN_C45_ADDR 0
703 #define MACB_MAN_C45_WRITE 1
704 #define MACB_MAN_C45_POST_READ_INCR 2
705 #define MACB_MAN_C45_READ 3
706 #define MACB_MAN_C45_CODE 2
707
708 /* Capability mask bits */
709 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
710 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
711 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
712 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
713 #define MACB_CAPS_USRIO_DISABLED 0x00000010
714 #define MACB_CAPS_JUMBO 0x00000020
715 #define MACB_CAPS_GEM_HAS_PTP 0x00000040
716 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080
717 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
718 #define MACB_CAPS_MIIONRGMII 0x00000200
719 #define MACB_CAPS_CLK_HW_CHG 0x04000000
720 #define MACB_CAPS_MACB_IS_EMAC 0x08000000
721 #define MACB_CAPS_FIFO_MODE 0x10000000
722 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
723 #define MACB_CAPS_SG_DISABLED 0x40000000
724 #define MACB_CAPS_MACB_IS_GEM 0x80000000
725 #define MACB_CAPS_PCS 0x01000000
726 #define MACB_CAPS_HIGH_SPEED 0x02000000
727
728 /* LSO settings */
729 #define MACB_LSO_UFO_ENABLE 0x01
730 #define MACB_LSO_TSO_ENABLE 0x02
731
732 /* Bit manipulation macros */
733 #define MACB_BIT(name) \
734 (1 << MACB_##name##_OFFSET)
735 #define MACB_BF(name,value) \
736 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
737 << MACB_##name##_OFFSET)
738 #define MACB_BFEXT(name,value)\
739 (((value) >> MACB_##name##_OFFSET) \
740 & ((1 << MACB_##name##_SIZE) - 1))
741 #define MACB_BFINS(name,value,old) \
742 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
743 << MACB_##name##_OFFSET)) \
744 | MACB_BF(name,value))
745
746 #define GEM_BIT(name) \
747 (1 << GEM_##name##_OFFSET)
748 #define GEM_BF(name, value) \
749 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
750 << GEM_##name##_OFFSET)
751 #define GEM_BFEXT(name, value)\
752 (((value) >> GEM_##name##_OFFSET) \
753 & ((1 << GEM_##name##_SIZE) - 1))
754 #define GEM_BFINS(name, value, old) \
755 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
756 << GEM_##name##_OFFSET)) \
757 | GEM_BF(name, value))
758
759 /* Register access macros */
760 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
761 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
762 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
763 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
764 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
765 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
766 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
767 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
768
769 #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */
770
771 /* Conditional GEM/MACB macros. These perform the operation to the correct
772 * register dependent on whether the device is a GEM or a MACB. For registers
773 * and bitfields that are common across both devices, use macb_{read,write}l
774 * to avoid the cost of the conditional.
775 */
776 #define macb_or_gem_writel(__bp, __reg, __value) \
777 ({ \
778 if (macb_is_gem((__bp))) \
779 gem_writel((__bp), __reg, __value); \
780 else \
781 macb_writel((__bp), __reg, __value); \
782 })
783
784 #define macb_or_gem_readl(__bp, __reg) \
785 ({ \
786 u32 __v; \
787 if (macb_is_gem((__bp))) \
788 __v = gem_readl((__bp), __reg); \
789 else \
790 __v = macb_readl((__bp), __reg); \
791 __v; \
792 })
793
794 #define MACB_READ_NSR(bp) macb_readl(bp, NSR)
795
796 /* struct macb_dma_desc - Hardware DMA descriptor
797 * @addr: DMA address of data buffer
798 * @ctrl: Control and status bits
799 */
800 struct macb_dma_desc {
801 u32 addr;
802 u32 ctrl;
803 };
804
805 #ifdef MACB_EXT_DESC
806 #define HW_DMA_CAP_32B 0
807 #define HW_DMA_CAP_64B (1 << 0)
808 #define HW_DMA_CAP_PTP (1 << 1)
809 #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
810
811 struct macb_dma_desc_64 {
812 u32 addrh;
813 u32 resvd;
814 };
815
816 struct macb_dma_desc_ptp {
817 u32 ts_1;
818 u32 ts_2;
819 };
820
821 struct gem_tx_ts {
822 struct sk_buff *skb;
823 struct macb_dma_desc_ptp desc_ptp;
824 };
825 #endif
826
827 /* DMA descriptor bitfields */
828 #define MACB_RX_USED_OFFSET 0
829 #define MACB_RX_USED_SIZE 1
830 #define MACB_RX_WRAP_OFFSET 1
831 #define MACB_RX_WRAP_SIZE 1
832 #define MACB_RX_WADDR_OFFSET 2
833 #define MACB_RX_WADDR_SIZE 30
834
835 #define MACB_RX_FRMLEN_OFFSET 0
836 #define MACB_RX_FRMLEN_SIZE 12
837 #define MACB_RX_OFFSET_OFFSET 12
838 #define MACB_RX_OFFSET_SIZE 2
839 #define MACB_RX_SOF_OFFSET 14
840 #define MACB_RX_SOF_SIZE 1
841 #define MACB_RX_EOF_OFFSET 15
842 #define MACB_RX_EOF_SIZE 1
843 #define MACB_RX_CFI_OFFSET 16
844 #define MACB_RX_CFI_SIZE 1
845 #define MACB_RX_VLAN_PRI_OFFSET 17
846 #define MACB_RX_VLAN_PRI_SIZE 3
847 #define MACB_RX_PRI_TAG_OFFSET 20
848 #define MACB_RX_PRI_TAG_SIZE 1
849 #define MACB_RX_VLAN_TAG_OFFSET 21
850 #define MACB_RX_VLAN_TAG_SIZE 1
851 #define MACB_RX_TYPEID_MATCH_OFFSET 22
852 #define MACB_RX_TYPEID_MATCH_SIZE 1
853 #define MACB_RX_SA4_MATCH_OFFSET 23
854 #define MACB_RX_SA4_MATCH_SIZE 1
855 #define MACB_RX_SA3_MATCH_OFFSET 24
856 #define MACB_RX_SA3_MATCH_SIZE 1
857 #define MACB_RX_SA2_MATCH_OFFSET 25
858 #define MACB_RX_SA2_MATCH_SIZE 1
859 #define MACB_RX_SA1_MATCH_OFFSET 26
860 #define MACB_RX_SA1_MATCH_SIZE 1
861 #define MACB_RX_EXT_MATCH_OFFSET 28
862 #define MACB_RX_EXT_MATCH_SIZE 1
863 #define MACB_RX_UHASH_MATCH_OFFSET 29
864 #define MACB_RX_UHASH_MATCH_SIZE 1
865 #define MACB_RX_MHASH_MATCH_OFFSET 30
866 #define MACB_RX_MHASH_MATCH_SIZE 1
867 #define MACB_RX_BROADCAST_OFFSET 31
868 #define MACB_RX_BROADCAST_SIZE 1
869
870 #define MACB_RX_FRMLEN_MASK 0xFFF
871 #define MACB_RX_JFRMLEN_MASK 0x3FFF
872
873 /* RX checksum offload disabled: bit 24 clear in NCFGR */
874 #define GEM_RX_TYPEID_MATCH_OFFSET 22
875 #define GEM_RX_TYPEID_MATCH_SIZE 2
876
877 /* RX checksum offload enabled: bit 24 set in NCFGR */
878 #define GEM_RX_CSUM_OFFSET 22
879 #define GEM_RX_CSUM_SIZE 2
880
881 #define MACB_TX_FRMLEN_OFFSET 0
882 #define MACB_TX_FRMLEN_SIZE 11
883 #define MACB_TX_LAST_OFFSET 15
884 #define MACB_TX_LAST_SIZE 1
885 #define MACB_TX_NOCRC_OFFSET 16
886 #define MACB_TX_NOCRC_SIZE 1
887 #define MACB_MSS_MFS_OFFSET 16
888 #define MACB_MSS_MFS_SIZE 14
889 #define MACB_TX_LSO_OFFSET 17
890 #define MACB_TX_LSO_SIZE 2
891 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19
892 #define MACB_TX_TCP_SEQ_SRC_SIZE 1
893 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
894 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
895 #define MACB_TX_UNDERRUN_OFFSET 28
896 #define MACB_TX_UNDERRUN_SIZE 1
897 #define MACB_TX_ERROR_OFFSET 29
898 #define MACB_TX_ERROR_SIZE 1
899 #define MACB_TX_WRAP_OFFSET 30
900 #define MACB_TX_WRAP_SIZE 1
901 #define MACB_TX_USED_OFFSET 31
902 #define MACB_TX_USED_SIZE 1
903
904 #define GEM_TX_FRMLEN_OFFSET 0
905 #define GEM_TX_FRMLEN_SIZE 14
906
907 /* Buffer descriptor constants */
908 #define GEM_RX_CSUM_NONE 0
909 #define GEM_RX_CSUM_IP_ONLY 1
910 #define GEM_RX_CSUM_IP_TCP 2
911 #define GEM_RX_CSUM_IP_UDP 3
912
913 /* limit RX checksum offload to TCP and UDP packets */
914 #define GEM_RX_CSUM_CHECKED_MASK 2
915
916 /* Scaled PPM fraction */
917 #define PPM_FRACTION 16
918
919 /* struct macb_tx_skb - data about an skb which is being transmitted
920 * @skb: skb currently being transmitted, only set for the last buffer
921 * of the frame
922 * @mapping: DMA address of the skb's fragment buffer
923 * @size: size of the DMA mapped buffer
924 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
925 * false when buffer was mapped with dma_map_single()
926 */
927 struct macb_tx_skb {
928 struct sk_buff *skb;
929 dma_addr_t mapping;
930 size_t size;
931 bool mapped_as_page;
932 };
933
934 /* Hardware-collected statistics. Used when updating the network
935 * device stats by a periodic timer.
936 */
937 struct macb_stats {
938 u32 rx_pause_frames;
939 u32 tx_ok;
940 u32 tx_single_cols;
941 u32 tx_multiple_cols;
942 u32 rx_ok;
943 u32 rx_fcs_errors;
944 u32 rx_align_errors;
945 u32 tx_deferred;
946 u32 tx_late_cols;
947 u32 tx_excessive_cols;
948 u32 tx_underruns;
949 u32 tx_carrier_errors;
950 u32 rx_resource_errors;
951 u32 rx_overruns;
952 u32 rx_symbol_errors;
953 u32 rx_oversize_pkts;
954 u32 rx_jabbers;
955 u32 rx_undersize_pkts;
956 u32 sqe_test_errors;
957 u32 rx_length_mismatch;
958 u32 tx_pause_frames;
959 };
960
961 struct gem_stats {
962 u32 tx_octets_31_0;
963 u32 tx_octets_47_32;
964 u32 tx_frames;
965 u32 tx_broadcast_frames;
966 u32 tx_multicast_frames;
967 u32 tx_pause_frames;
968 u32 tx_64_byte_frames;
969 u32 tx_65_127_byte_frames;
970 u32 tx_128_255_byte_frames;
971 u32 tx_256_511_byte_frames;
972 u32 tx_512_1023_byte_frames;
973 u32 tx_1024_1518_byte_frames;
974 u32 tx_greater_than_1518_byte_frames;
975 u32 tx_underrun;
976 u32 tx_single_collision_frames;
977 u32 tx_multiple_collision_frames;
978 u32 tx_excessive_collisions;
979 u32 tx_late_collisions;
980 u32 tx_deferred_frames;
981 u32 tx_carrier_sense_errors;
982 u32 rx_octets_31_0;
983 u32 rx_octets_47_32;
984 u32 rx_frames;
985 u32 rx_broadcast_frames;
986 u32 rx_multicast_frames;
987 u32 rx_pause_frames;
988 u32 rx_64_byte_frames;
989 u32 rx_65_127_byte_frames;
990 u32 rx_128_255_byte_frames;
991 u32 rx_256_511_byte_frames;
992 u32 rx_512_1023_byte_frames;
993 u32 rx_1024_1518_byte_frames;
994 u32 rx_greater_than_1518_byte_frames;
995 u32 rx_undersized_frames;
996 u32 rx_oversize_frames;
997 u32 rx_jabbers;
998 u32 rx_frame_check_sequence_errors;
999 u32 rx_length_field_frame_errors;
1000 u32 rx_symbol_errors;
1001 u32 rx_alignment_errors;
1002 u32 rx_resource_errors;
1003 u32 rx_overruns;
1004 u32 rx_ip_header_checksum_errors;
1005 u32 rx_tcp_checksum_errors;
1006 u32 rx_udp_checksum_errors;
1007 };
1008
1009 /* Describes the name and offset of an individual statistic register, as
1010 * returned by `ethtool -S`. Also describes which net_device_stats statistics
1011 * this register should contribute to.
1012 */
1013 struct gem_statistic {
1014 char stat_string[ETH_GSTRING_LEN];
1015 int offset;
1016 u32 stat_bits;
1017 };
1018
1019 /* Bitfield defs for net_device_stat statistics */
1020 #define GEM_NDS_RXERR_OFFSET 0
1021 #define GEM_NDS_RXLENERR_OFFSET 1
1022 #define GEM_NDS_RXOVERERR_OFFSET 2
1023 #define GEM_NDS_RXCRCERR_OFFSET 3
1024 #define GEM_NDS_RXFRAMEERR_OFFSET 4
1025 #define GEM_NDS_RXFIFOERR_OFFSET 5
1026 #define GEM_NDS_TXERR_OFFSET 6
1027 #define GEM_NDS_TXABORTEDERR_OFFSET 7
1028 #define GEM_NDS_TXCARRIERERR_OFFSET 8
1029 #define GEM_NDS_TXFIFOERR_OFFSET 9
1030 #define GEM_NDS_COLLISIONS_OFFSET 10
1031
1032 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
1033 #define GEM_STAT_TITLE_BITS(name, title, bits) { \
1034 .stat_string = title, \
1035 .offset = GEM_##name, \
1036 .stat_bits = bits \
1037 }
1038
1039 /* list of gem statistic registers. The names MUST match the
1040 * corresponding GEM_* definitions.
1041 */
1042 static const struct gem_statistic gem_statistics[] = {
1043 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
1044 GEM_STAT_TITLE(TXCNT, "tx_frames"),
1045 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
1046 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
1047 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
1048 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
1049 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
1050 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
1051 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
1052 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
1053 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
1054 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
1055 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
1056 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
1057 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
1058 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1059 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
1060 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1061 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
1062 GEM_BIT(NDS_TXERR)|
1063 GEM_BIT(NDS_TXABORTEDERR)|
1064 GEM_BIT(NDS_COLLISIONS)),
1065 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
1066 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1067 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
1068 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
1069 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1070 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
1071 GEM_STAT_TITLE(RXCNT, "rx_frames"),
1072 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
1073 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
1074 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
1075 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
1076 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
1077 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
1078 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
1079 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
1080 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
1081 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1082 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1083 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1084 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1085 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1086 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1087 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1088 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1089 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1090 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1091 GEM_BIT(NDS_RXERR)),
1092 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1093 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1094 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1095 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1096 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1097 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1098 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1099 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1100 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1101 GEM_BIT(NDS_RXERR)),
1102 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1103 GEM_BIT(NDS_RXERR)),
1104 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1105 GEM_BIT(NDS_RXERR)),
1106 };
1107
1108 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1109
1110 #define QUEUE_STAT_TITLE(title) { \
1111 .stat_string = title, \
1112 }
1113
1114 /* per queue statistics, each should be unsigned long type */
1115 struct queue_stats {
1116 union {
1117 unsigned long first;
1118 unsigned long rx_packets;
1119 };
1120 unsigned long rx_bytes;
1121 unsigned long rx_dropped;
1122 unsigned long tx_packets;
1123 unsigned long tx_bytes;
1124 unsigned long tx_dropped;
1125 };
1126
1127 static const struct gem_statistic queue_statistics[] = {
1128 QUEUE_STAT_TITLE("rx_packets"),
1129 QUEUE_STAT_TITLE("rx_bytes"),
1130 QUEUE_STAT_TITLE("rx_dropped"),
1131 QUEUE_STAT_TITLE("tx_packets"),
1132 QUEUE_STAT_TITLE("tx_bytes"),
1133 QUEUE_STAT_TITLE("tx_dropped"),
1134 };
1135
1136 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1137
1138 struct macb;
1139 struct macb_queue;
1140
1141 struct macb_or_gem_ops {
1142 int (*mog_alloc_rx_buffers)(struct macb *bp);
1143 void (*mog_free_rx_buffers)(struct macb *bp);
1144 void (*mog_init_rings)(struct macb *bp);
1145 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
1146 int budget);
1147 };
1148
1149 /* MACB-PTP interface: adapt to platform needs. */
1150 struct macb_ptp_info {
1151 void (*ptp_init)(struct net_device *ndev);
1152 void (*ptp_remove)(struct net_device *ndev);
1153 s32 (*get_ptp_max_adj)(void);
1154 unsigned int (*get_tsu_rate)(struct macb *bp);
1155 int (*get_ts_info)(struct net_device *dev,
1156 struct ethtool_ts_info *info);
1157 int (*get_hwtst)(struct net_device *netdev,
1158 struct ifreq *ifr);
1159 int (*set_hwtst)(struct net_device *netdev,
1160 struct ifreq *ifr, int cmd);
1161 };
1162
1163 struct macb_pm_data {
1164 u32 scrt2;
1165 u32 usrio;
1166 };
1167
1168 struct macb_usrio_config {
1169 u32 mii;
1170 u32 rmii;
1171 u32 rgmii;
1172 u32 refclk;
1173 u32 hdfctlen;
1174 };
1175
1176 struct macb_config {
1177 u32 caps;
1178 unsigned int dma_burst_length;
1179 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1180 struct clk **hclk, struct clk **tx_clk,
1181 struct clk **rx_clk, struct clk **tsu_clk);
1182 int (*init)(struct platform_device *pdev);
1183 int jumbo_max_len;
1184 const struct macb_usrio_config *usrio;
1185 };
1186
1187 struct tsu_incr {
1188 u32 sub_ns;
1189 u32 ns;
1190 };
1191
1192 struct macb_queue {
1193 struct macb *bp;
1194 int irq;
1195
1196 unsigned int ISR;
1197 unsigned int IER;
1198 unsigned int IDR;
1199 unsigned int IMR;
1200 unsigned int TBQP;
1201 unsigned int TBQPH;
1202 unsigned int RBQS;
1203 unsigned int RBQP;
1204 unsigned int RBQPH;
1205
1206 unsigned int tx_head, tx_tail;
1207 struct macb_dma_desc *tx_ring;
1208 struct macb_tx_skb *tx_skb;
1209 dma_addr_t tx_ring_dma;
1210 struct work_struct tx_error_task;
1211
1212 dma_addr_t rx_ring_dma;
1213 dma_addr_t rx_buffers_dma;
1214 unsigned int rx_tail;
1215 unsigned int rx_prepared_head;
1216 struct macb_dma_desc *rx_ring;
1217 struct sk_buff **rx_skbuff;
1218 void *rx_buffers;
1219 struct napi_struct napi;
1220 struct queue_stats stats;
1221
1222 #ifdef CONFIG_MACB_USE_HWSTAMP
1223 struct work_struct tx_ts_task;
1224 unsigned int tx_ts_head, tx_ts_tail;
1225 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
1226 #endif
1227 };
1228
1229 struct ethtool_rx_fs_item {
1230 struct ethtool_rx_flow_spec fs;
1231 struct list_head list;
1232 };
1233
1234 struct ethtool_rx_fs_list {
1235 struct list_head list;
1236 unsigned int count;
1237 };
1238
1239 struct macb {
1240 void __iomem *regs;
1241 bool native_io;
1242
1243 /* hardware IO accessors */
1244 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1245 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1246
1247 size_t rx_buffer_size;
1248
1249 unsigned int rx_ring_size;
1250 unsigned int tx_ring_size;
1251
1252 unsigned int num_queues;
1253 unsigned int queue_mask;
1254 struct macb_queue queues[MACB_MAX_QUEUES];
1255
1256 spinlock_t lock;
1257 struct platform_device *pdev;
1258 struct clk *pclk;
1259 struct clk *hclk;
1260 struct clk *tx_clk;
1261 struct clk *rx_clk;
1262 struct clk *tsu_clk;
1263 struct net_device *dev;
1264 union {
1265 struct macb_stats macb;
1266 struct gem_stats gem;
1267 } hw_stats;
1268
1269 struct macb_or_gem_ops macbgem_ops;
1270
1271 struct mii_bus *mii_bus;
1272 struct phylink *phylink;
1273 struct phylink_config phylink_config;
1274 struct phylink_pcs phylink_pcs;
1275
1276 u32 caps;
1277 unsigned int dma_burst_length;
1278
1279 phy_interface_t phy_interface;
1280
1281 /* AT91RM9200 transmit queue (1 on wire + 1 queued) */
1282 struct macb_tx_skb rm9200_txq[2];
1283 unsigned int max_tx_length;
1284
1285 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1286
1287 unsigned int rx_frm_len_mask;
1288 unsigned int jumbo_max_len;
1289
1290 u32 wol;
1291
1292 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1293 #ifdef MACB_EXT_DESC
1294 uint8_t hw_dma_cap;
1295 #endif
1296 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1297 unsigned int tsu_rate;
1298 struct ptp_clock *ptp_clock;
1299 struct ptp_clock_info ptp_clock_info;
1300 struct tsu_incr tsu_incr;
1301 struct hwtstamp_config tstamp_config;
1302
1303 /* RX queue filer rule set*/
1304 struct ethtool_rx_fs_list rx_fs_list;
1305 spinlock_t rx_fs_lock;
1306 unsigned int max_tuples;
1307
1308 struct tasklet_struct hresp_err_tasklet;
1309
1310 int rx_bd_rd_prefetch;
1311 int tx_bd_rd_prefetch;
1312
1313 u32 rx_intr_mask;
1314
1315 struct macb_pm_data pm_data;
1316 const struct macb_usrio_config *usrio;
1317 };
1318
1319 #ifdef CONFIG_MACB_USE_HWSTAMP
1320 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1321 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1322 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1323
1324 enum macb_bd_control {
1325 TSTAMP_DISABLED,
1326 TSTAMP_FRAME_PTP_EVENT_ONLY,
1327 TSTAMP_ALL_PTP_FRAMES,
1328 TSTAMP_ALL_FRAMES,
1329 };
1330
1331 void gem_ptp_init(struct net_device *ndev);
1332 void gem_ptp_remove(struct net_device *ndev);
1333 int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1334 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
gem_ptp_do_txstamp(struct macb_queue * queue,struct sk_buff * skb,struct macb_dma_desc * desc)1335 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1336 {
1337 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1338 return -ENOTSUPP;
1339
1340 return gem_ptp_txstamp(queue, skb, desc);
1341 }
1342
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1343 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1344 {
1345 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1346 return;
1347
1348 gem_ptp_rxstamp(bp, skb, desc);
1349 }
1350 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1351 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1352 #else
gem_ptp_init(struct net_device * ndev)1353 static inline void gem_ptp_init(struct net_device *ndev) { }
gem_ptp_remove(struct net_device * ndev)1354 static inline void gem_ptp_remove(struct net_device *ndev) { }
1355
gem_ptp_do_txstamp(struct macb_queue * queue,struct sk_buff * skb,struct macb_dma_desc * desc)1356 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1357 {
1358 return -1;
1359 }
1360
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1361 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1362 #endif
1363
macb_is_gem(struct macb * bp)1364 static inline bool macb_is_gem(struct macb *bp)
1365 {
1366 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1367 }
1368
gem_has_ptp(struct macb * bp)1369 static inline bool gem_has_ptp(struct macb *bp)
1370 {
1371 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1372 }
1373
1374 /**
1375 * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration
1376 * @pclk: platform clock
1377 * @hclk: AHB clock
1378 */
1379 struct macb_platform_data {
1380 struct clk *pclk;
1381 struct clk *hclk;
1382 };
1383
1384 #endif /* _MACB_H */
1385