/linux/drivers/gpu/drm/amd/display/dc/inc/ |
A D | core_types.h | 211 struct mem_input *mis[MAX_PIPES]; 212 struct hubp *hubps[MAX_PIPES]; 215 struct dpp *dpps[MAX_PIPES]; 222 struct dce_aux *engines[MAX_PIPES]; 223 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 224 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 259 struct dc_3dlut *mpc_lut[MAX_PIPES]; 291 struct abm *multiple_abms[MAX_PIPES]; 405 struct pipe_ctx pipe_ctx[MAX_PIPES]; 407 bool is_audio_acquired[MAX_PIPES]; [all …]
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/linux/drivers/gpu/drm/amd/display/dc/core/ |
A D | dc_link_enc_cfg.c | 111 for (i = 0; i < MAX_PIPES; i++) { in remove_link_enc_assignment() 246 for (i = 0; i < MAX_PIPES; i++) { in clear_enc_assignments() 294 for (i = 0; i < MAX_PIPES; i++) in link_enc_cfg_link_encs_assign() 377 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign() 423 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_stream_using_link_enc() 463 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_link_enc_used_by_link() 485 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_next_avail_link_enc() 519 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_is_link_enc_avail() 549 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_validate() 562 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_validate() [all …]
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A D | dc_stream.c | 267 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes() 367 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position() 566 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter() 594 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp() 625 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos() 652 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done() 658 if (i == MAX_PIPES) in dc_stream_dmdata_status_done() 680 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata() 686 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
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A D | dc.c | 420 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_adjust_vmin_vmax() 456 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_last_used_drr_vtotal() 486 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crtc_position() 531 if (i == MAX_PIPES) in dc_stream_forward_dmcu_crc_window() 565 if (i == MAX_PIPES) in dc_stream_stop_dmcu_crc_win_update() 603 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_configure_crc() 609 if (i == MAX_PIPES) in dc_stream_configure_crc() 668 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crc() 674 if (i == MAX_PIPES) in dc_stream_get_crc() 692 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dyn_expansion() [all …]
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A D | dc_debug.c | 312 int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0}; in context_timing_trace()
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A D | dc_link_hwss.c | 104 for (i = 0; i < MAX_PIPES; i++) { in dp_enable_link_phy() 437 for (i = 0; i < MAX_PIPES; i++) { in dp_retrain_link_dp_test() 895 for (i = 0; i < MAX_PIPES; i++) {
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A D | dc_resource.c | 606 for (i = 0; i < MAX_PIPES; i++) { in resource_find_used_clk_src_for_sharing() 1210 for (i = 0; i < MAX_PIPES; i++) { in resource_build_scaling_params_for_context() 1286 for (i = 0; i < MAX_PIPES; i++) { in resource_get_head_pipe_for_stream() 2684 for (i = 0; i < MAX_PIPES; i++) { in dc_resource_state_copy_construct()
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A D | dc_link.c | 2856 for (i = 0; i < MAX_PIPES; i++) { in get_abm_from_stream_res() 2903 for (i = 0; i < MAX_PIPES; i++) { in get_pipe_from_link() 3104 for (i = 0; i < MAX_PIPES; i++) { in dc_link_setup_psr() 4566 for (i = 0; i < MAX_PIPES; i++) { 4577 if (i == MAX_PIPES)
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
A D | dcn20_dccg.h | 132 type OTG_ADD_PIXEL[MAX_PIPES];\ 133 type OTG_DROP_PIXEL[MAX_PIPES]; 166 type DTBCLK_DTO_ENABLE[MAX_PIPES];\ 167 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\ 168 type PIPE_DTO_SRC_SEL[MAX_PIPES];\ 169 type DTBCLK_DTO_DIV[MAX_PIPES];\ 213 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; 220 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; 221 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
A D | opp.h | 200 int dpp[MAX_PIPES]; 201 int mpcc[MAX_PIPES]; 209 bool mpcc_disconnect_pending[MAX_PIPES];
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A D | dccg.h | 61 int pipe_dppclk_khz[MAX_PIPES]; 63 int dtbclk_khz[MAX_PIPES];
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A D | hw_shared.h | 38 #define MAX_PIPES 6 macro
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A D | clk_mgr_internal.h | 297 unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
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/linux/drivers/gpu/drm/amd/display/dc/dce/ |
A D | dce_clock_source.h | 222 uint32_t PHASE[MAX_PIPES]; 223 uint32_t MODULO[MAX_PIPES]; 224 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
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A D | dmub_psr.c | 34 #define MAX_PIPES 6 macro 265 for (i = 0; i < MAX_PIPES; i++) { in dmub_psr_copy_settings()
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A D | dce_clk_mgr.c | 189 for (i = 0; i < MAX_PIPES; i++) { in get_max_pixel_clock_for_all_paths() 508 for (k = 0; k < MAX_PIPES; k++) in dce110_fill_display_configs()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
A D | amdgpu_dm_mst_types.c | 606 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp() 607 int initial_slack[MAX_PIPES]; in increase_dsc_bpp() 704 bool tried[MAX_PIPES]; in try_disable_dsc() 705 int kbps_increase[MAX_PIPES]; in try_disable_dsc() 772 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link() 953 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
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A D | amdgpu_dm_debugfs.c | 1313 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_read() 1415 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_write() 1500 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_read() 1600 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_write() 1685 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_read() 1785 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_write() 1866 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_read() 1963 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_write() 2042 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_width_read() 2099 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_height_read() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
A D | dce110_clk_mgr.c | 134 for (k = 0; k < MAX_PIPES; k++) in dce110_fill_display_configs()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
A D | dce_clk_mgr.c | 170 for (i = 0; i < MAX_PIPES; i++) { in dce_get_max_pixel_clock_for_all_paths()
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/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
A D | dcn21_resource.c | 1192 int split[MAX_PIPES] = { 0 }; in dcn21_fast_validate_bw() 1256 for (i = 0; i < MAX_PIPES; i++) in dcn21_fast_validate_bw() 1341 int pipe_split_from[MAX_PIPES]; in dcn21_validate_bandwidth_fp()
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/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
A D | dce110_hw_sequencer.c | 1100 for (i = 0; i < MAX_PIPES; i++) { in dce110_enable_audio_stream() 1905 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 1946 for (i = 0; i < MAX_PIPES; i++) { 2140 for (i = 0; i < MAX_PIPES; i++) {
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
A D | dcn20_clk_mgr.c | 508 for (i = 0; i < MAX_PIPES * 2; i++) { in dcn2_notify_link_rate_change()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
A D | dcn30_clk_mgr.c | 490 for (i = 0; i < MAX_PIPES * 2; i++) { in dcn30_notify_link_rate_change()
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
A D | dcn10_hw_sequencer.c | 1128 TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES); in dcn10_verify_allow_pstate_change_high() 2060 struct dc_crtc_timing hw_crtc_timing[MAX_PIPES] = {0}; in dcn10_align_pixel_clocks() 2061 uint64_t phase[MAX_PIPES]; in dcn10_align_pixel_clocks() 2062 uint64_t modulo[MAX_PIPES]; in dcn10_align_pixel_clocks() 3177 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { in dcn10_wait_for_mpcc_disconnect()
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