Searched refs:MCFSIM_ICR1 (Results 1 – 7 of 7) sorted by relevance
| /linux/arch/m68k/coldfire/ |
| A D | intc-5272.c | 46 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
47 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
48 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
49 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
50 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
51 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
52 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
53 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
166 writel(0x88888888, MCFSIM_ICR1); in init_IRQ()
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| /linux/arch/m68k/include/asm/ |
| A D | m5407sim.h | 39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ macro
114 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
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| A D | m5307sim.h | 39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ macro
150 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
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| A D | m525xsim.h | 43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ macro
145 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
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| A D | m5272sim.h | 31 #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ macro
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| A D | m5206sim.h | 26 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */ macro
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| A D | m53xxsim.h | 52 #define MCFSIM_ICR1 0xFC048041 macro
68 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
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