1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Motion Eye video4linux driver for Sony Vaio PictureBook
4  *
5  * Copyright (C) 2001-2004 Stelian Pop <stelian@popies.net>
6  *
7  * Copyright (C) 2001-2002 Alcôve <www.alcove.com>
8  *
9  * Copyright (C) 2000 Andrew Tridgell <tridge@valinux.com>
10  *
11  * Earlier work by Werner Almesberger, Paul `Rusty' Russell and Paul Mackerras.
12  *
13  * Some parts borrowed from various video4linux drivers, especially
14  * bttv-driver.c and zoran.c, see original files for credits.
15  */
16 
17 #ifndef _MEYE_PRIV_H_
18 #define _MEYE_PRIV_H_
19 
20 #define MEYE_DRIVER_MAJORVERSION	 1
21 #define MEYE_DRIVER_MINORVERSION	14
22 
23 #define MEYE_DRIVER_VERSION __stringify(MEYE_DRIVER_MAJORVERSION) "." \
24 			    __stringify(MEYE_DRIVER_MINORVERSION)
25 
26 #include <linux/types.h>
27 #include <linux/pci.h>
28 #include <linux/kfifo.h>
29 #include <media/v4l2-ctrls.h>
30 
31 /****************************************************************************/
32 /* Motion JPEG chip registers                                               */
33 /****************************************************************************/
34 
35 /* Motion JPEG chip PCI configuration registers */
36 #define MCHIP_PCI_POWER_CSR		0x54
37 #define MCHIP_PCI_MCORE_STATUS		0x60		/* see HIC_STATUS   */
38 #define MCHIP_PCI_HOSTUSEREQ_SET	0x64
39 #define MCHIP_PCI_HOSTUSEREQ_CLR	0x68
40 #define MCHIP_PCI_LOWPOWER_SET		0x6c
41 #define MCHIP_PCI_LOWPOWER_CLR		0x70
42 #define MCHIP_PCI_SOFTRESET_SET		0x74
43 
44 /* Motion JPEG chip memory mapped registers */
45 #define MCHIP_MM_REGS			0x200		/* 512 bytes        */
46 #define MCHIP_REG_TIMEOUT		1000		/* reg access, ~us  */
47 #define MCHIP_MCC_VRJ_TIMEOUT		1000		/* MCC & VRJ access */
48 
49 #define MCHIP_MM_PCI_MODE		0x00		/* PCI access mode */
50 #define MCHIP_MM_PCI_MODE_RETRY		0x00000001	/* retry mode */
51 #define MCHIP_MM_PCI_MODE_MASTER	0x00000002	/* master access */
52 #define MCHIP_MM_PCI_MODE_READ_LINE	0x00000004	/* read line */
53 
54 #define MCHIP_MM_INTA			0x04		/* Int status/mask */
55 #define MCHIP_MM_INTA_MCC		0x00000001	/* MCC interrupt */
56 #define MCHIP_MM_INTA_VRJ		0x00000002	/* VRJ interrupt */
57 #define MCHIP_MM_INTA_HIC_1		0x00000004	/* one frame done */
58 #define MCHIP_MM_INTA_HIC_1_MASK	0x00000400	/* 1: enable */
59 #define MCHIP_MM_INTA_HIC_END		0x00000008	/* all frames done */
60 #define MCHIP_MM_INTA_HIC_END_MASK	0x00000800
61 #define MCHIP_MM_INTA_JPEG		0x00000010	/* decompress. error */
62 #define MCHIP_MM_INTA_JPEG_MASK		0x00001000
63 #define MCHIP_MM_INTA_CAPTURE		0x00000020	/* capture end */
64 #define MCHIP_MM_INTA_PCI_ERR		0x00000040	/* PCI error */
65 #define MCHIP_MM_INTA_PCI_ERR_MASK	0x00004000
66 
67 #define MCHIP_MM_PT_ADDR		0x08		/* page table address*/
68 							/* n*4kB */
69 #define MCHIP_NB_PAGES			1024		/* pages for display */
70 #define MCHIP_NB_PAGES_MJPEG		256		/* pages for mjpeg */
71 
72 #define MCHIP_MM_FIR(n)			(0x0c+(n)*4)	/* Frame info 0-3 */
73 #define MCHIP_MM_FIR_RDY		0x00000001	/* frame ready */
74 #define MCHIP_MM_FIR_FAILFR_MASK	0xf8000000	/* # of failed frames */
75 #define MCHIP_MM_FIR_FAILFR_SHIFT	27
76 
77 	/* continuous comp/decomp mode */
78 #define MCHIP_MM_FIR_C_ENDL_MASK	0x000007fe	/* end DW [10] */
79 #define MCHIP_MM_FIR_C_ENDL_SHIFT	1
80 #define MCHIP_MM_FIR_C_ENDP_MASK	0x0007f800	/* end page [8] */
81 #define MCHIP_MM_FIR_C_ENDP_SHIFT	11
82 #define MCHIP_MM_FIR_C_STARTP_MASK	0x07f80000	/* start page [8] */
83 #define MCHIP_MM_FIR_C_STARTP_SHIFT	19
84 
85 	/* continuous picture output mode */
86 #define MCHIP_MM_FIR_O_STARTP_MASK	0x7ffe0000	/* start page [10] */
87 #define MCHIP_MM_FIR_O_STARTP_SHIFT	17
88 
89 #define MCHIP_MM_FIFO_DATA		0x1c		/* PCI TGT FIFO data */
90 #define MCHIP_MM_FIFO_STATUS		0x20		/* PCI TGT FIFO stat */
91 #define MCHIP_MM_FIFO_MASK		0x00000003
92 #define MCHIP_MM_FIFO_WAIT_OR_READY	0x00000002      /* Bits common to WAIT & READY*/
93 #define MCHIP_MM_FIFO_IDLE		0x0		/* HIC idle */
94 #define MCHIP_MM_FIFO_IDLE1		0x1		/* idem ??? */
95 #define	MCHIP_MM_FIFO_WAIT		0x2		/* wait request */
96 #define MCHIP_MM_FIFO_READY		0x3		/* data ready */
97 
98 #define MCHIP_HIC_HOST_USEREQ		0x40		/* host uses MCORE */
99 
100 #define MCHIP_HIC_TP_BUSY		0x44		/* taking picture */
101 
102 #define MCHIP_HIC_PIC_SAVED		0x48		/* pic in SDRAM */
103 
104 #define MCHIP_HIC_LOWPOWER		0x4c		/* clock stopped */
105 
106 #define MCHIP_HIC_CTL			0x50		/* HIC control */
107 #define MCHIP_HIC_CTL_SOFT_RESET	0x00000001	/* MCORE reset */
108 #define MCHIP_HIC_CTL_MCORE_RDY		0x00000002	/* MCORE ready */
109 
110 #define MCHIP_HIC_CMD			0x54		/* HIC command */
111 #define MCHIP_HIC_CMD_BITS		0x00000003      /* cmd width=[1:0]*/
112 #define MCHIP_HIC_CMD_NOOP		0x0
113 #define MCHIP_HIC_CMD_START		0x1
114 #define MCHIP_HIC_CMD_STOP		0x2
115 
116 #define MCHIP_HIC_MODE			0x58
117 #define MCHIP_HIC_MODE_NOOP		0x0
118 #define MCHIP_HIC_MODE_STILL_CAP	0x1		/* still pic capt */
119 #define MCHIP_HIC_MODE_DISPLAY		0x2		/* display */
120 #define MCHIP_HIC_MODE_STILL_COMP	0x3		/* still pic comp. */
121 #define MCHIP_HIC_MODE_STILL_DECOMP	0x4		/* still pic decomp. */
122 #define MCHIP_HIC_MODE_CONT_COMP	0x5		/* cont capt+comp */
123 #define MCHIP_HIC_MODE_CONT_DECOMP	0x6		/* cont decomp+disp */
124 #define MCHIP_HIC_MODE_STILL_OUT	0x7		/* still pic output */
125 #define MCHIP_HIC_MODE_CONT_OUT		0x8		/* cont output */
126 
127 #define MCHIP_HIC_STATUS		0x5c
128 #define MCHIP_HIC_STATUS_MCC_RDY	0x00000001	/* MCC reg acc ok */
129 #define MCHIP_HIC_STATUS_VRJ_RDY	0x00000002	/* VRJ reg acc ok */
130 #define MCHIP_HIC_STATUS_IDLE           0x00000003
131 #define MCHIP_HIC_STATUS_CAPDIS		0x00000004	/* cap/disp in prog */
132 #define MCHIP_HIC_STATUS_COMPDEC	0x00000008	/* (de)comp in prog */
133 #define MCHIP_HIC_STATUS_BUSY		0x00000010	/* HIC busy */
134 
135 #define MCHIP_HIC_S_RATE		0x60		/* MJPEG # frames */
136 
137 #define MCHIP_HIC_PCI_VFMT		0x64		/* video format */
138 #define MCHIP_HIC_PCI_VFMT_YVYU		0x00000001	/* 0: V Y' U Y */
139 							/* 1: Y' V Y U */
140 
141 #define MCHIP_MCC_CMD			0x80		/* MCC commands */
142 #define MCHIP_MCC_CMD_INITIAL		0x0		/* idle ? */
143 #define MCHIP_MCC_CMD_IIC_START_SET	0x1
144 #define MCHIP_MCC_CMD_IIC_END_SET	0x2
145 #define MCHIP_MCC_CMD_FM_WRITE		0x3		/* frame memory */
146 #define MCHIP_MCC_CMD_FM_READ		0x4
147 #define MCHIP_MCC_CMD_FM_STOP		0x5
148 #define MCHIP_MCC_CMD_CAPTURE		0x6
149 #define MCHIP_MCC_CMD_DISPLAY		0x7
150 #define MCHIP_MCC_CMD_END_DISP		0x8
151 #define MCHIP_MCC_CMD_STILL_COMP	0x9
152 #define MCHIP_MCC_CMD_STILL_DECOMP	0xa
153 #define MCHIP_MCC_CMD_STILL_OUTPUT	0xb
154 #define MCHIP_MCC_CMD_CONT_OUTPUT	0xc
155 #define MCHIP_MCC_CMD_CONT_COMP		0xd
156 #define MCHIP_MCC_CMD_CONT_DECOMP	0xe
157 #define MCHIP_MCC_CMD_RESET		0xf		/* MCC reset */
158 
159 #define MCHIP_MCC_IIC_WR		0x84
160 
161 #define MCHIP_MCC_MCC_WR		0x88
162 
163 #define MCHIP_MCC_MCC_RD		0x8c
164 
165 #define MCHIP_MCC_STATUS		0x90
166 #define MCHIP_MCC_STATUS_CAPT		0x00000001	/* capturing */
167 #define MCHIP_MCC_STATUS_DISP		0x00000002	/* displaying */
168 #define MCHIP_MCC_STATUS_COMP		0x00000004	/* compressing */
169 #define MCHIP_MCC_STATUS_DECOMP		0x00000008	/* decompressing */
170 #define MCHIP_MCC_STATUS_MCC_WR		0x00000010	/* register ready */
171 #define MCHIP_MCC_STATUS_MCC_RD		0x00000020	/* register ready */
172 #define MCHIP_MCC_STATUS_IIC_WR		0x00000040	/* register ready */
173 #define MCHIP_MCC_STATUS_OUTPUT		0x00000080	/* output in prog */
174 
175 #define MCHIP_MCC_SIG_POLARITY		0x94
176 #define MCHIP_MCC_SIG_POL_VS_H		0x00000001	/* VS active-high */
177 #define MCHIP_MCC_SIG_POL_HS_H		0x00000002	/* HS active-high */
178 #define MCHIP_MCC_SIG_POL_DOE_H		0x00000004	/* DOE active-high */
179 
180 #define MCHIP_MCC_IRQ			0x98
181 #define MCHIP_MCC_IRQ_CAPDIS_STRT	0x00000001	/* cap/disp started */
182 #define MCHIP_MCC_IRQ_CAPDIS_STRT_MASK	0x00000010
183 #define MCHIP_MCC_IRQ_CAPDIS_END	0x00000002	/* cap/disp ended */
184 #define MCHIP_MCC_IRQ_CAPDIS_END_MASK	0x00000020
185 #define MCHIP_MCC_IRQ_COMPDEC_STRT	0x00000004	/* (de)comp started */
186 #define MCHIP_MCC_IRQ_COMPDEC_STRT_MASK	0x00000040
187 #define MCHIP_MCC_IRQ_COMPDEC_END	0x00000008	/* (de)comp ended */
188 #define MCHIP_MCC_IRQ_COMPDEC_END_MASK	0x00000080
189 
190 #define MCHIP_MCC_HSTART		0x9c		/* video in */
191 #define MCHIP_MCC_VSTART		0xa0
192 #define MCHIP_MCC_HCOUNT		0xa4
193 #define MCHIP_MCC_VCOUNT		0xa8
194 #define MCHIP_MCC_R_XBASE		0xac		/* capt/disp */
195 #define MCHIP_MCC_R_YBASE		0xb0
196 #define MCHIP_MCC_R_XRANGE		0xb4
197 #define MCHIP_MCC_R_YRANGE		0xb8
198 #define MCHIP_MCC_B_XBASE		0xbc		/* comp/decomp */
199 #define MCHIP_MCC_B_YBASE		0xc0
200 #define MCHIP_MCC_B_XRANGE		0xc4
201 #define MCHIP_MCC_B_YRANGE		0xc8
202 
203 #define MCHIP_MCC_R_SAMPLING		0xcc		/* 1: 1:4 */
204 
205 #define MCHIP_VRJ_CMD			0x100		/* VRJ commands */
206 
207 /* VRJ registers (see table 12.2.4) */
208 #define MCHIP_VRJ_COMPRESSED_DATA	0x1b0
209 #define MCHIP_VRJ_PIXEL_DATA		0x1b8
210 
211 #define MCHIP_VRJ_BUS_MODE		0x100
212 #define MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL	0x108
213 #define MCHIP_VRJ_PDAT_USE		0x110
214 #define MCHIP_VRJ_MODE_SPECIFY		0x118
215 #define MCHIP_VRJ_LIMIT_COMPRESSED_LO	0x120
216 #define MCHIP_VRJ_LIMIT_COMPRESSED_HI	0x124
217 #define MCHIP_VRJ_COMP_DATA_FORMAT	0x128
218 #define MCHIP_VRJ_TABLE_DATA		0x140
219 #define MCHIP_VRJ_RESTART_INTERVAL	0x148
220 #define MCHIP_VRJ_NUM_LINES		0x150
221 #define MCHIP_VRJ_NUM_PIXELS		0x158
222 #define MCHIP_VRJ_NUM_COMPONENTS	0x160
223 #define MCHIP_VRJ_SOF1			0x168
224 #define MCHIP_VRJ_SOF2			0x170
225 #define MCHIP_VRJ_SOF3			0x178
226 #define MCHIP_VRJ_SOF4			0x180
227 #define MCHIP_VRJ_SOS			0x188
228 #define MCHIP_VRJ_SOFT_RESET		0x190
229 
230 #define MCHIP_VRJ_STATUS		0x1c0
231 #define MCHIP_VRJ_STATUS_BUSY		0x00001
232 #define MCHIP_VRJ_STATUS_COMP_ACCESS	0x00002
233 #define MCHIP_VRJ_STATUS_PIXEL_ACCESS	0x00004
234 #define MCHIP_VRJ_STATUS_ERROR		0x00008
235 
236 #define MCHIP_VRJ_IRQ_FLAG		0x1c8
237 #define MCHIP_VRJ_ERROR_REPORT		0x1d8
238 
239 #define MCHIP_VRJ_START_COMMAND		0x1a0
240 
241 /****************************************************************************/
242 /* Driver definitions.                                                      */
243 /****************************************************************************/
244 
245 /* Sony Programmable I/O Controller for accessing the camera commands */
246 #include <linux/sony-laptop.h>
247 
248 /* private API definitions */
249 #include <linux/meye.h>
250 #include <linux/mutex.h>
251 
252 
253 /* Enable jpg software correction */
254 #define MEYE_JPEG_CORRECTION	1
255 
256 /* Maximum size of a buffer */
257 #define MEYE_MAX_BUFSIZE	614400	/* 640 * 480 * 2 */
258 
259 /* Maximum number of buffers */
260 #define MEYE_MAX_BUFNBRS	32
261 
262 /* State of a buffer */
263 #define MEYE_BUF_UNUSED	0	/* not used */
264 #define MEYE_BUF_USING	1	/* currently grabbing / playing */
265 #define MEYE_BUF_DONE	2	/* done */
266 
267 /* grab buffer */
268 struct meye_grab_buffer {
269 	int state;			/* state of buffer */
270 	unsigned long size;		/* size of jpg frame */
271 	u64 ts;				/* timestamp */
272 	unsigned long sequence;		/* sequence number */
273 };
274 
275 /* size of kfifos containing buffer indices */
276 #define MEYE_QUEUE_SIZE	MEYE_MAX_BUFNBRS
277 
278 /* Motion Eye device structure */
279 struct meye {
280 	struct v4l2_device v4l2_dev;	/* Main v4l2_device struct */
281 	struct v4l2_ctrl_handler hdl;
282 	struct pci_dev *mchip_dev;	/* pci device */
283 	u8 mchip_irq;			/* irq */
284 	u8 mchip_mode;			/* actual mchip mode: HIC_MODE... */
285 	u8 mchip_fnum;			/* current mchip frame number */
286 	unsigned char __iomem *mchip_mmregs;/* mchip: memory mapped registers */
287 	u8 *mchip_ptable[MCHIP_NB_PAGES];/* mchip: ptable */
288 	void *mchip_ptable_toc;		/* mchip: ptable toc */
289 	dma_addr_t mchip_dmahandle;	/* mchip: dma handle to ptable toc */
290 	unsigned char *grab_fbuffer;	/* capture framebuffer */
291 	unsigned char *grab_temp;	/* temporary buffer */
292 					/* list of buffers */
293 	struct meye_grab_buffer grab_buffer[MEYE_MAX_BUFNBRS];
294 	int vma_use_count[MEYE_MAX_BUFNBRS]; /* mmap count */
295 	struct mutex lock;		/* mutex for open/mmap... */
296 	struct kfifo grabq;		/* queue for buffers to be grabbed */
297 	spinlock_t grabq_lock;		/* lock protecting the queue */
298 	struct kfifo doneq;		/* queue for grabbed buffers */
299 	spinlock_t doneq_lock;		/* lock protecting the queue */
300 	wait_queue_head_t proc_list;	/* wait queue */
301 	struct video_device vdev;	/* video device parameters */
302 	u16 brightness;
303 	u16 hue;
304 	u16 contrast;
305 	u16 colour;
306 	struct meye_params params;	/* additional parameters */
307 	unsigned long in_use;		/* set to 1 if the device is in use */
308 	u8 pm_mchip_mode;		/* old mchip mode */
309 };
310 
311 #endif
312