Searched refs:MCLK (Results 1 – 25 of 63) sorted by relevance
123
| /linux/Documentation/devicetree/bindings/sound/ |
| A D | mt8173-rt5650.txt | 16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
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| A D | cs42l56.txt | 20 Frequency = MCLK / 4 * (N+2)
22 MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.
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| A D | cirrus,cs42l51.yaml | 27 - const: MCLK
63 clock-names = "MCLK";
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| A D | tas2552.txt | 18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
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| A D | maxim,max98088.txt | 12 - clocks: the clock provider of MCLK, see ../clock/clock-bindings.txt section
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| A D | max9860.txt | 14 - clocks : A clock specifier for the clock connected as MCLK.
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| A D | everest,es8316.yaml | 22 - description: clock for master clock (MCLK)
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| A D | st,stm32-sai.yaml | 81 - description: MCLK clock from a SAI set as master clock provider.
87 - const: MCLK
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| A D | cirrus,cs35l41.yaml | 98 3 = MCLK input
123 3 = MCLK input
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| A D | da7213.txt | 10 - clocks : phandle and clock specifier for codec MCLK.
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| A D | cs4271.txt | 24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
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| A D | tas571x.txt | 22 - clocks: clock phandle for the MCLK input
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| A D | st,stm32-i2s.yaml | 58 description: Configure the I2S device as MCLK clock provider.
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| A D | cs43130.txt | 20 When external MCLK is generated by external crystal
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| /linux/Documentation/devicetree/bindings/media/ |
| A D | pxa-camera.txt | 12 sensor master clock MCLK
13 - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
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| /linux/sound/soc/meson/ |
| A D | aiu-encoder-spdif.c | 144 ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate); in aiu_encoder_spdif_hw_params()
183 ret = clk_set_parent(aiu->spdif.clks[MCLK].clk, in aiu_encoder_spdif_startup()
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| A D | aiu-encoder-i2s.c | 153 fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate); in aiu_encoder_i2s_set_clocks()
279 ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq); in aiu_encoder_i2s_set_sysclk()
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| A D | aiu.h | 20 MCLK, enumerator
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| A D | aiu.c | 205 [MCLK] = "i2s_mclk",
212 [MCLK] = "spdif_mclk_sel"
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| /linux/drivers/spi/ |
| A D | spi-mpc52xx-psc.c | 27 #define MCLK 20000000 /* PSC port MClk in hz */ macro
104 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
106 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
315 mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; in mpc52xx_psc_spi_port_config()
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| /linux/Documentation/sound/soc/ |
| A D | clocking.rst | 12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
34 - BCLK = MCLK / x, or
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| /linux/drivers/media/pci/ddbridge/ |
| A D | ddbridge-sx8.c | 23 static const u32 MCLK = (1550000000 / 12); variable
196 if (p->symbol_rate >= (MCLK / 2)) in start()
218 if (p->symbol_rate >= MCLK / 2) { in start()
253 i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7; in start()
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| A D | sii902x.txt | 31 Describes SII902x MCLK input. MCLK can be used to produce
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| /linux/arch/arm/boot/dts/ |
| A D | stm32mp15xx-dkx.dtsi | 77 "Playback" , "MCLK",
78 "Capture" , "MCLK",
213 clock-names = "MCLK";
523 clock-names = "sai_ck", "MCLK";
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | fsl,sai-clock.yaml | 18 clock of the second SAI as a MCLK clock for an audio codec, for example.
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