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Searched refs:MC_SEQ_WR_CTL_D1_LP (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/radeon/
A Dbtcd.h152 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
A Dbtc_dpm.c1880 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in btc_check_s0_mc_reg_index()
2035 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in btc_initialize_mc_reg_table()
A Dnid.h810 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
A Dsid.h578 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
A Dcikd.h703 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
A Devergreend.h328 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 macro
A Dni_dpm.c2796 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in ni_check_s0_mc_reg_index()
2892 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in ni_initialize_mc_reg_table()
A Dcypress_dpm.c998 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; in cypress_set_mc_reg_address_table()
A Dci_dpm.c4415 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in ci_check_s0_mc_reg_index()
4613 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in ci_initialize_mc_reg_table()
A Dsi_dpm.c5433 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in si_check_s0_mc_reg_index()
5533 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in si_initialize_mc_reg_table()
/linux/drivers/gpu/drm/amd/amdgpu/
A Dsid.h579 #define MC_SEQ_WR_CTL_D1_LP 0xAA0 macro
/linux/drivers/gpu/drm/amd/pm/powerplay/
A Dsi_dpm.c5886 *out_reg = MC_SEQ_WR_CTL_D1_LP; in si_check_s0_mc_reg_index()
5986 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in si_initialize_mc_reg_table()

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