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Searched refs:MDIO_MMD_VEND1 (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/net/phy/
A Dnxp-c45-tja11xx.c559 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
589 { "phy_symbol_error_cnt", MDIO_MMD_VEND1,
595 { "phy_link_loss_cnt", MDIO_MMD_VEND1,
597 { "phy_link_failure_cnt", MDIO_MMD_VEND1,
599 { "r_good_frame_cnt", MDIO_MMD_VEND1,
601 { "r_bad_frame_cnt", MDIO_MMD_VEND1,
603 { "r_rxer_frame_cnt", MDIO_MMD_VEND1,
605 { "rx_preamble_count", MDIO_MMD_VEND1,
607 { "tx_preamble_count", MDIO_MMD_VEND1,
609 { "rx_ipg_length", MDIO_MMD_VEND1,
[all …]
A Dmediatek-ge.c40 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); in mtk_gephy_config_init()
43 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); in mtk_gephy_config_init()
65 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); in mt7531_phy_config_init()
68 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); in mt7531_phy_config_init()
69 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); in mt7531_phy_config_init()
A Dadin.c251 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode()
287 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode()
297 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
314 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
519 if (devad == MDIO_MMD_VEND1) in adin_cl45_to_adin_reg()
687 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_soft_reset()
696 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, in adin_soft_reset()
723 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1); in adin_read_mmd_stat_regs()
732 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2); in adin_read_mmd_stat_regs()
840 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, in adin_cable_test_report_pair()
[all …]
A Daquantia_main.c262 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, in aqr_config_intr()
267 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, in aqr_config_intr()
468 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in aqr107_wait_reset_complete()
478 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); in aqr107_chip_info()
485 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); in aqr107_chip_info()
579 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); in aqr107_link_change_notify()
590 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_suspend()
596 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_resume()
A Dteranetics.c39 if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93)) in teranetics_aneg_done()
54 if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93)) { in teranetics_read_status()
A Daquantia_hwmon.c58 int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); in aqr_hwmon_get()
79 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); in aqr_hwmon_set()
84 int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); in aqr_hwmon_test_bit()
A Dmxl-gpy.c158 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_2500basex_chk()
167 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); in gpy_sgmii_aneg_en()
254 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_config_aneg()
273 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_update_interface()
289 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, in gpy_update_interface()
A Dbcm84881.c197 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011); in bcm84881_read_status()
A Dphy_device.c728 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
766 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
/linux/drivers/net/ethernet/chelsio/cxgb3/
A Daq100x.c71 int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000); in aq100x_reset()
86 err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL); in aq100x_intr_enable()
92 return t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, 0); in aq100x_intr_disable()
99 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v); in aq100x_intr_clear()
110 err = t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &cause); in aq100x_intr_handler()
292 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
319 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v); in t3_aq100x_phy_prep()
328 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
332 err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1, in t3_aq100x_phy_prep()
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
A Dmacsec_api.c83 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
86 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
94 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
97 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
108 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_ingress_record()
137 ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in get_raw_ingress_record()
180 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_egress_record()
183 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_egress_record()
190 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_egress_record()
192 aq_mss_mdio_write(hw, MDIO_MMD_VEND1, in set_raw_egress_record()
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/
A Daq_phy.c165 val = aq_phy_read_reg(aq_hw, MDIO_MMD_VEND1, in aq_phy_disable_ptp()
168 aq_phy_write_reg(aq_hw, MDIO_MMD_VEND1, in aq_phy_disable_ptp()
/linux/include/uapi/linux/
A Dmdio.h27 #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ macro
139 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
/linux/drivers/net/dsa/mv88e6xxx/
A Dserdes.c1423 { MDIO_MMD_VEND1, 0x8093, 0xcb5a, 0xffff }, in mv88e6393x_serdes_erratum_5_2()
1424 { MDIO_MMD_VEND1, 0x8171, 0x7088, 0xffff }, in mv88e6393x_serdes_erratum_5_2()
1425 { MDIO_MMD_VEND1, 0x80c9, 0x311a, 0xffff }, in mv88e6393x_serdes_erratum_5_2()
1426 { MDIO_MMD_VEND1, 0x80a2, 0x8000, 0xff7f }, in mv88e6393x_serdes_erratum_5_2()
1427 { MDIO_MMD_VEND1, 0x80a9, 0x0000, 0xfff0 }, in mv88e6393x_serdes_erratum_5_2()
1428 { MDIO_MMD_VEND1, 0x80a3, 0x0000, 0xf8ff }, in mv88e6393x_serdes_erratum_5_2()
1502 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_VEND1, 0x8000, 0x58); in mv88e6393x_serdes_fix_2500basex_an()
/linux/drivers/net/ethernet/intel/ixgbe/
A Dixgbe_x550.c2338 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2346 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2355 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2370 MDIO_MMD_VEND1, in ixgbe_get_lasi_ext_t_x550em()
2450 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2459 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2466 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2475 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
2482 MDIO_MMD_VEND1, in ixgbe_enable_lasi_ext_t_x550em()
3335 MDIO_MMD_VEND1, in ixgbe_init_ext_t_x550em()
[all …]
A Dixgbe_phy.c1173 MDIO_MMD_VEND1, in ixgbe_check_phy_link_tnx()
2654 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg); in ixgbe_set_copper_phy_power()
2666 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg); in ixgbe_set_copper_phy_power()
/linux/drivers/net/dsa/sja1105/
A Dsja1105_mdio.c25 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read()
55 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write()

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