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Searched refs:MDIO_MMD_VEND2 (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/net/pcs/
A Dpcs-xpcs-nxp.c74 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL2, in nxp_sja1105_sgmii_pma_config()
89 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0, in nxp_sja1110_pma_config()
94 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1, in nxp_sja1110_pma_config()
100 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER1_0, in nxp_sja1110_pma_config()
107 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_0, val); in nxp_sja1110_pma_config()
122 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_TRIM, val); in nxp_sja1110_pma_config()
127 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DATAPATH_1, 0); in nxp_sja1110_pma_config()
134 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0, in nxp_sja1110_pma_config()
139 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL1, in nxp_sja1110_pma_config()
155 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE); in nxp_sja1110_pma_config()
[all …]
A Dpcs-xpcs.c242 dev = MDIO_MMD_VEND2; in xpcs_soft_reset()
388 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); in xpcs_config_usxgmii()
395 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); in xpcs_config_usxgmii()
728 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, in xpcs_config_aneg_c37_sgmii()
734 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); in xpcs_config_aneg_c37_sgmii()
749 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); in xpcs_config_aneg_c37_sgmii()
763 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, in xpcs_config_aneg_c37_sgmii()
782 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); in xpcs_config_2500basex()
975 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); in xpcs_link_up_sgmii()
1015 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); in xpcs_get_id()
[all …]
A Dpcs-lynx.c41 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); in lynx_pcs_get_state_usxgmii()
50 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); in lynx_pcs_get_state_usxgmii()
178 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, in lynx_pcs_config_usxgmii()
/linux/drivers/net/phy/
A Dintel-xway.c255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_config_init()
259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_config_init()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_config_init()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_config_init()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_config_init()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_config_init()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_config_init()
277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_config_init()
A Dmarvell10g.c181 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); in mv3310_hwmon_read_temp_reg()
258 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
265 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, in mv3310_hwmon_config()
1155 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); in mv3110_get_wol()
1170 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1177 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1184 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1191 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1199 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1207 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
[all …]
A Dmxl-gpy.c394 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
401 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
408 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
421 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
435 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
471 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL); in gpy_get_wol()
A Dmarvell-88x2222.c81 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
86 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
208 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
A Dphy_device.c728 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
766 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
/linux/drivers/net/ethernet/amd/xgbe/
A Dxgbe-mdio.c151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_clear_interrupts()
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_clear_interrupts()
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_disable_interrupts()
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_disable_interrupts()
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_enable_interrupts()
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_enable_interrupts()
356 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
365 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
648 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_isr()
970 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_init()
[all …]
A Dxgbe-phy-v2.c1582 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); in xgbe_phy_an37_outcome()
1583 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); in xgbe_phy_an37_outcome()
/linux/drivers/net/dsa/sja1105/
A Dsja1105_mdio.c25 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read()
28 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1105_pcs_mdio_read()
30 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1105_pcs_mdio_read()
55 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write()
81 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1110_pcs_mdio_read()
83 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1110_pcs_mdio_read()
A Dsja1105_main.c2218 u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1); in sja1105_static_config_reload()
/linux/include/uapi/linux/
A Dmdio.h28 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ macro
140 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
/linux/drivers/net/dsa/
A Dmt7530.c146 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); in core_write()
159 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); in core_rmw()
162 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); in core_rmw()
2321 MDIO_MMD_VEND2, CORE_PLL_GROUP4); in mt7531_setup()
2324 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, in mt7531_setup()

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