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Searched refs:MHZ (Results 1 – 25 of 68) sorted by relevance

123

/linux/drivers/clk/samsung/
A Dclk-s3c2410.c130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
132 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
133 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
134 PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
144 PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
145 PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
149 PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
150 PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
341 if (_get_rate("xti") == 12 * MHZ) { in s3c2410_common_clk_init()
[all …]
A Dclk-exynos3250.c670 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
671 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
672 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
673 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
674 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
675 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
677 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
678 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
680 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
[all …]
A Dclk-exynos4.c1104 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1105 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1106 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1107 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1108 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1109 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1110 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1111 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1112 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
1113 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
[all …]
A Dclk-exynos5420.c1400 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1401 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1422 PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
1423 PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
1424 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
1425 PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
1426 PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
1427 PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
1428 PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
1429 PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
[all …]
A Dclk-exynos5250.c693 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
722 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
723 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
724 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
725 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
726 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
727 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
728 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
729 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
804 if (_get_rate("fin_pll") == 24 * MHZ) { in exynos5250_clk_init()
[all …]
A Dclk-exynos5260.c23 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
24 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
25 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
26 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
27 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
28 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
29 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
31 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
32 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
33 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
[all …]
A Dclk-exynos5410.c227 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
228 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
229 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
230 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
231 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
232 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
233 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
234 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
235 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
236 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
[all …]
A Dclk-exynos5433.c715 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
716 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
717 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
718 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
722 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
723 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
724 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
/linux/Documentation/userspace-api/media/dvb/
A Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
38 - .. _BANDWIDTH-5-MHZ:
46 - .. _BANDWIDTH-6-MHZ:
54 - .. _BANDWIDTH-7-MHZ:
62 - .. _BANDWIDTH-8-MHZ:
70 - .. _BANDWIDTH-10-MHZ:
/linux/drivers/clk/
A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/linux/arch/mips/ralink/
A Dmt7620.c64 #define MHZ(x) ((x) * 1000 * 1000) macro
73 return MHZ(40); in mt7620_get_xtal_rate()
75 return MHZ(20); in mt7620_get_xtal_rate()
87 return MHZ(40); in mt7620_get_periph_rate()
104 return MHZ(600); in mt7620_get_cpu_pll_rate()
130 return MHZ(480); in mt7620_get_pll_rate()
208 if (xtal_rate == MHZ(40)) in ralink_clk_init()
209 cpu_rate = MHZ(580); in ralink_clk_init()
211 cpu_rate = MHZ(575); in ralink_clk_init()
213 periph_rate = MHZ(40); in ralink_clk_init()
[all …]
/linux/drivers/net/can/softing/
A Dsofting_cs.c26 #define MHZ (1000*1000) macro
33 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
45 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
57 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
69 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
81 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
93 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
105 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
117 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
129 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
/linux/Documentation/devicetree/bindings/spi/
A Dspi-slave-mt27xx.txt17 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
19 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
20 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
21 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
A Dspi-mt65xx.txt30 - <&clk26m>: specify parent clock 26MHZ.
31 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
33 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
34 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
35 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
/linux/arch/arm/mach-s3c/
A Dsetup-usb-phy-s3c64xx.c36 case 12 * MHZ: in s3c_usb_otgphy_init()
39 case 24 * MHZ: in s3c_usb_otgphy_init()
43 case 48 * MHZ: in s3c_usb_otgphy_init()
A Dcpu.h80 #ifndef MHZ
81 #define MHZ (1000*1000) macro
84 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/linux/drivers/clk/mediatek/
A Dclk-mt2701.c30 108 * MHZ),
32 400 * MHZ),
36 340 * MHZ),
38 340 * MHZ),
40 340 * MHZ),
42 27 * MHZ),
44 416 * MHZ),
46 143 * MHZ),
48 27 * MHZ),
915 #define MT8590_PLL_FMAX (2000 * MHZ)
A Dclk-mt8183.c1064 #define MT8183_PLL_FMAX (3800UL * MHZ)
1065 #define MT8183_PLL_FMIN (1500UL * MHZ)
1107 { .div = 1, .freq = 1500 * MHZ },
1108 { .div = 2, .freq = 750 * MHZ },
1109 { .div = 3, .freq = 375 * MHZ },
1116 { .div = 1, .freq = 1600 * MHZ },
1117 { .div = 2, .freq = 800 * MHZ },
1118 { .div = 3, .freq = 400 * MHZ },
1119 { .div = 4, .freq = 200 * MHZ },
/linux/drivers/gpu/drm/exynos/
A Dexynos_drm_dsi.c538 #ifndef MHZ
539 #define MHZ (1000*1000) macro
553 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); in exynos_dsi_pll_find_pms()
554 p_max = fin / (6 * MHZ); in exynos_dsi_pll_find_pms()
569 if (tmp < 500 * MHZ || in exynos_dsi_pll_find_pms()
570 tmp > driver_data->max_freq * MHZ) in exynos_dsi_pll_find_pms()
622 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, in exynos_dsi_set_pll()
623 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, in exynos_dsi_set_pll()
624 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, in exynos_dsi_set_pll()
625 770 * MHZ, 870 * MHZ, 950 * MHZ, in exynos_dsi_set_pll()
[all …]
/linux/drivers/phy/samsung/
A Dphy-exynos4x12-usb2.c140 case 10 * MHZ: in exynos4x12_rate_to_clk()
143 case 12 * MHZ: in exynos4x12_rate_to_clk()
149 case 20 * MHZ: in exynos4x12_rate_to_clk()
152 case 24 * MHZ: in exynos4x12_rate_to_clk()
155 case 50 * MHZ: in exynos4x12_rate_to_clk()
A Dphy-s5pv210-usb2.c73 case 12 * MHZ: in s5pv210_rate_to_clk()
76 case 24 * MHZ: in s5pv210_rate_to_clk()
79 case 48 * MHZ: in s5pv210_rate_to_clk()
A Dphy-exynos5250-usb2.c149 case 10 * MHZ: in exynos5250_rate_to_clk()
152 case 12 * MHZ: in exynos5250_rate_to_clk()
158 case 20 * MHZ: in exynos5250_rate_to_clk()
161 case 24 * MHZ: in exynos5250_rate_to_clk()
164 case 50 * MHZ: in exynos5250_rate_to_clk()
/linux/drivers/clk/hisilicon/
A Dclk-hi3660-stub.c25 #define MHZ (1000 * 1000) macro
66 stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; in hi3660_stub_clk_recalc_rate()
86 stub_clk->msg[1] = rate / MHZ; in hi3660_stub_clk_set_rate()
/linux/drivers/soc/samsung/
A Dexynos-asv.c23 #define MHZ 1000000U macro
49 opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true); in exynos_asv_update_cpu_opps()
64 ret = dev_pm_opp_adjust_voltage(cpu, opp_freq * MHZ, in exynos_asv_update_cpu_opps()
/linux/arch/powerpc/boot/
A Ddevtree.c61 #define MHZ(x) ((x + 500000) / 1000000) macro
67 printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu)); in dt_fixup_cpu_clocks()
68 printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb)); in dt_fixup_cpu_clocks()
70 printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus)); in dt_fixup_cpu_clocks()
87 printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq)); in dt_fixup_clock()

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