1 // SPDX-License-Identifier: GPL-2.0
2 /* Qualcomm IPQ8064 MDIO interface driver
3  *
4  * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
5  * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
6  */
7 
8 #include <linux/delay.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_mdio.h>
12 #include <linux/of_address.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 
16 /* MII address register definitions */
17 #define MII_ADDR_REG_ADDR			0x10
18 #define MII_BUSY				BIT(0)
19 #define MII_WRITE				BIT(1)
20 #define MII_CLKRANGE(x)				((x) << 2)
21 #define MII_CLKRANGE_60_100M			MII_CLKRANGE(0)
22 #define MII_CLKRANGE_100_150M			MII_CLKRANGE(1)
23 #define MII_CLKRANGE_20_35M			MII_CLKRANGE(2)
24 #define MII_CLKRANGE_35_60M			MII_CLKRANGE(3)
25 #define MII_CLKRANGE_150_250M			MII_CLKRANGE(4)
26 #define MII_CLKRANGE_250_300M			MII_CLKRANGE(5)
27 #define MII_CLKRANGE_MASK			GENMASK(4, 2)
28 #define MII_REG_SHIFT				6
29 #define MII_REG_MASK				GENMASK(10, 6)
30 #define MII_ADDR_SHIFT				11
31 #define MII_ADDR_MASK				GENMASK(15, 11)
32 
33 #define MII_DATA_REG_ADDR			0x14
34 
35 #define MII_MDIO_DELAY_USEC			(1000)
36 #define MII_MDIO_RETRY_MSEC			(10)
37 
38 struct ipq8064_mdio {
39 	struct regmap *base; /* NSS_GMAC0_BASE */
40 };
41 
42 static int
ipq8064_mdio_wait_busy(struct ipq8064_mdio * priv)43 ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
44 {
45 	u32 busy;
46 
47 	return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
48 					!(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
49 					MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
50 }
51 
52 static int
ipq8064_mdio_read(struct mii_bus * bus,int phy_addr,int reg_offset)53 ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
54 {
55 	u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
56 	struct ipq8064_mdio *priv = bus->priv;
57 	u32 ret_val;
58 	int err;
59 
60 	/* Reject clause 45 */
61 	if (reg_offset & MII_ADDR_C45)
62 		return -EOPNOTSUPP;
63 
64 	miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
65 		   ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
66 
67 	regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
68 	usleep_range(10, 13);
69 
70 	err = ipq8064_mdio_wait_busy(priv);
71 	if (err)
72 		return err;
73 
74 	regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
75 	return (int)ret_val;
76 }
77 
78 static int
ipq8064_mdio_write(struct mii_bus * bus,int phy_addr,int reg_offset,u16 data)79 ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
80 {
81 	u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
82 	struct ipq8064_mdio *priv = bus->priv;
83 
84 	/* Reject clause 45 */
85 	if (reg_offset & MII_ADDR_C45)
86 		return -EOPNOTSUPP;
87 
88 	regmap_write(priv->base, MII_DATA_REG_ADDR, data);
89 
90 	miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
91 		   ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
92 
93 	regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
94 
95 	/* For the specific reg 31 extra time is needed or the next
96 	 * read will produce garbage data.
97 	 */
98 	if (reg_offset == 31)
99 		usleep_range(30, 43);
100 	else
101 		usleep_range(10, 13);
102 
103 	return ipq8064_mdio_wait_busy(priv);
104 }
105 
106 static const struct regmap_config ipq8064_mdio_regmap_config = {
107 	.reg_bits = 32,
108 	.reg_stride = 4,
109 	.val_bits = 32,
110 	.can_multi_write = false,
111 	/* the mdio lock is used by any user of this mdio driver */
112 	.disable_locking = true,
113 
114 	.cache_type = REGCACHE_NONE,
115 };
116 
117 static int
ipq8064_mdio_probe(struct platform_device * pdev)118 ipq8064_mdio_probe(struct platform_device *pdev)
119 {
120 	struct device_node *np = pdev->dev.of_node;
121 	struct ipq8064_mdio *priv;
122 	struct resource res;
123 	struct mii_bus *bus;
124 	void __iomem *base;
125 	int ret;
126 
127 	if (of_address_to_resource(np, 0, &res))
128 		return -ENOMEM;
129 
130 	base = ioremap(res.start, resource_size(&res));
131 	if (!base)
132 		return -ENOMEM;
133 
134 	bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
135 	if (!bus)
136 		return -ENOMEM;
137 
138 	bus->name = "ipq8064_mdio_bus";
139 	bus->read = ipq8064_mdio_read;
140 	bus->write = ipq8064_mdio_write;
141 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
142 	bus->parent = &pdev->dev;
143 
144 	priv = bus->priv;
145 	priv->base = devm_regmap_init_mmio(&pdev->dev, base,
146 					   &ipq8064_mdio_regmap_config);
147 	if (IS_ERR(priv->base))
148 		return PTR_ERR(priv->base);
149 
150 	ret = of_mdiobus_register(bus, np);
151 	if (ret)
152 		return ret;
153 
154 	platform_set_drvdata(pdev, bus);
155 	return 0;
156 }
157 
158 static int
ipq8064_mdio_remove(struct platform_device * pdev)159 ipq8064_mdio_remove(struct platform_device *pdev)
160 {
161 	struct mii_bus *bus = platform_get_drvdata(pdev);
162 
163 	mdiobus_unregister(bus);
164 
165 	return 0;
166 }
167 
168 static const struct of_device_id ipq8064_mdio_dt_ids[] = {
169 	{ .compatible = "qcom,ipq8064-mdio" },
170 	{ }
171 };
172 MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
173 
174 static struct platform_driver ipq8064_mdio_driver = {
175 	.probe = ipq8064_mdio_probe,
176 	.remove = ipq8064_mdio_remove,
177 	.driver = {
178 		.name = "ipq8064-mdio",
179 		.of_match_table = ipq8064_mdio_dt_ids,
180 	},
181 };
182 
183 module_platform_driver(ipq8064_mdio_driver);
184 
185 MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
186 MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
187 MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
188 MODULE_LICENSE("GPL");
189