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Searched refs:MIPS_CONF5_MSAEN (Results 1 – 4 of 4) sorted by relevance

/linux/arch/mips/include/asm/
A Dmsa.h100 set_c0_config5(MIPS_CONF5_MSAEN); in enable_msa()
108 clear_c0_config5(MIPS_CONF5_MSAEN); in disable_msa()
118 return read_c0_config5() & MIPS_CONF5_MSAEN; in is_msa_enabled()
A Dmipsregs.h695 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) macro
/linux/arch/mips/kvm/
A Dmips.c1378 read_c0_config5() & MIPS_CONF5_MSAEN) in kvm_mips_handle_exit()
1460 set_c0_config5(MIPS_CONF5_MSAEN); in kvm_own_msa()
A Dvz.c116 mask |= MIPS_CONF5_MSAEN; in kvm_vz_config5_guest_wrmask()
1606 !(read_gc0_config5() & MIPS_CONF5_MSAEN) || in kvm_trap_vz_handle_msa_disabled()
3164 MIPS_CONF5_MSAEN | in kvm_vz_vcpu_setup()

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